Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Martin Roth | 3b2653b | 2013-02-24 10:46:11 -0700 | [diff] [blame] | 3 | |
| 4 | #ifndef _NB_AGESA_CHIP_H_ |
| 5 | #define _NB_AGESA_CHIP_H_ |
| 6 | |
| 7 | struct northbridge_amd_agesa_family14_config |
| 8 | { |
| 9 | /* |
| 10 | * Here is an example of how this would be put into the devicetree.cb file |
| 11 | * Note that only Socket 0, Channel 0 is used for the Ontario |
| 12 | * (family 14, Fam 0x00-0x0F) parts. |
| 13 | * This should be placed after the device pci 18.x statements |
| 14 | * |
| 15 | * register "spdAddrLookup" = " |
| 16 | * { // Use 8-bit SPD addresses here |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 17 | * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 |
| 18 | * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) |
Martin Roth | 3b2653b | 2013-02-24 10:46:11 -0700 | [diff] [blame] | 19 | * }" |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | u8 spdAddrLookup[2][2][4]; |
| 24 | }; |
| 25 | |
| 26 | #endif |