AMD Fam14: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F14 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper. The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories. The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.
Notes:
This started by duplicating what was in Persimmon, and was changed to
use the devicetree.cb structures. The ASF setup was also removed from
the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed
for the SPD access and doesn't make sense to initialize here.
Significant cleanup and magic number reduction was done as well.
It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.
This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper
Yes, it would make sense to split this into two separate files
and move the SMBUS initialization and access into the southbridge
wrapper. Maybe that can come next.
Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2497
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
new file mode 100644
index 0000000..56d9c92
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _NB_AGESA_CHIP_H_
+#define _NB_AGESA_CHIP_H_
+
+struct northbridge_amd_agesa_family14_config
+{
+ /*
+ * Here is an example of how this would be put into the devicetree.cb file
+ * Note that only Socket 0, Channel 0 is used for the Ontario
+ * (family 14, Fam 0x00-0x0F) parts.
+ * This should be placed after the device pci 18.x statements
+ *
+ * register "spdAddrLookup" = "
+ * { // Use 8-bit SPD addresses here
+ * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
+ * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
+ * }"
+ *
+ */
+
+ u8 spdAddrLookup[2][2][4];
+};
+
+#endif