Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 18 | #define __SIMPLE_DEVICE__ |
| 19 | |
Duncan Laurie | 2e79009 | 2016-09-19 12:05:49 -0700 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 21 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 22 | #include <device/mmio.h> |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 23 | #include <cbmem.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 24 | #include <console/console.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 25 | #include <cpu/x86/msr.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 28 | #include <device/pci_def.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 29 | #include <intelblocks/msr.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 30 | #include <intelblocks/pmclib.h> |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 31 | #include <intelblocks/rtc.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 32 | #include <intelblocks/tco.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 33 | #include <soc/iomap.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 34 | #include <soc/cpu.h> |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 35 | #include <soc/pci_devs.h> |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 36 | #include <soc/pm.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 37 | #include <soc/smbus.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 38 | #include <security/vboot/vbnv.h> |
Elyes HAOUAS | add76f9 | 2019-03-21 09:55:49 +0100 | [diff] [blame] | 39 | |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 40 | #include "chip.h" |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 41 | |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 42 | static uintptr_t read_pmc_mmio_bar(void) |
| 43 | { |
Lijian Zhao | 9108680 | 2016-09-06 18:15:29 -0700 | [diff] [blame] | 44 | return PMC_BAR0; |
Alexandru Gagniuc | a633980 | 2016-04-05 12:40:24 -0700 | [diff] [blame] | 45 | } |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 46 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 47 | uintptr_t soc_read_pmc_base(void) |
Shaunak Saha | 9a0c9ac | 2016-06-27 23:00:15 -0700 | [diff] [blame] | 48 | { |
| 49 | return read_pmc_mmio_bar(); |
| 50 | } |
| 51 | |
Michael Niewöhner | b4d960b | 2019-11-02 12:14:06 +0100 | [diff] [blame] | 52 | uint32_t *soc_pmc_etr_addr(void) |
| 53 | { |
| 54 | return (uint32_t *)(soc_read_pmc_base() + ETR); |
| 55 | } |
| 56 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 57 | const char *const *soc_smi_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 58 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 59 | static const char *const smi_sts_bits[] = { |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 60 | [BIOS_SMI_STS] = "BIOS", |
| 61 | [LEGACY_USB_SMI_STS] = "LEGACY USB", |
| 62 | [SLP_SMI_STS] = "SLP_SMI", |
| 63 | [APM_SMI_STS] = "APM", |
| 64 | [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 65 | [FAKE_PM1_SMI_STS] = "PM1", |
Lee Leahy | 320b7ca | 2017-03-09 09:42:48 -0800 | [diff] [blame] | 66 | [GPIO_SMI_STS] = "GPIO_SMI", |
| 67 | [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI", |
Aaron Durbin | 7929dd0 | 2016-06-10 18:01:45 -0500 | [diff] [blame] | 68 | [MC_SMI_STS] = "MCSMI", |
| 69 | [TCO_SMI_STS] = "TCO", |
| 70 | [PERIODIC_SMI_STS] = "PERIODIC", |
| 71 | [SERIRQ_SMI_STS] = "SERIRQ", |
| 72 | [SMBUS_SMI_STS] = "SMBUS_SMI", |
| 73 | [XHCI_SMI_STS] = "XHCI", |
| 74 | [HSMBUS_SMI_STS] = "HOST_SMBUS", |
| 75 | [SCS_SMI_STS] = "SCS", |
| 76 | [PCIE_SMI_STS] = "PCI_EXP_SMI", |
| 77 | [SCC2_SMI_STS] = "SCC2", |
| 78 | [SPI_SSMI_STS] = "SPI_SSMI", |
| 79 | [SPI_SMI_STS] = "SPI", |
| 80 | [PMC_OCP_SMI_STS] = "OCP_CSE", |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 81 | }; |
| 82 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 83 | *a = ARRAY_SIZE(smi_sts_bits); |
| 84 | return smi_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 85 | } |
| 86 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 87 | /* |
| 88 | * For APL/GLK this check for power button status if nothing else |
| 89 | * is indicating an SMI and SMIs aren't turned into SCIs. |
| 90 | * Apparently, there is no PM1 status bit in the SMI status |
| 91 | * register. That makes things difficult for |
| 92 | * determining if the power button caused an SMI. |
| 93 | */ |
| 94 | uint32_t soc_get_smi_status(uint32_t generic_sts) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 95 | { |
Furquan Shaikh | 43810d9 | 2017-10-16 22:22:46 -0700 | [diff] [blame] | 96 | if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 97 | uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 98 | |
| 99 | /* Fake PM1 status bit if power button pressed. */ |
| 100 | if (pm1_sts & PWRBTN_STS) |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 101 | generic_sts |= (1 << FAKE_PM1_SMI_STS); |
Aaron Durbin | a554b71 | 2016-06-10 18:04:21 -0500 | [diff] [blame] | 102 | } |
| 103 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 104 | return generic_sts; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 105 | } |
| 106 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 107 | const char *const *soc_tco_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 108 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 109 | static const char *const tco_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 110 | [3] = "TIMEOUT", |
| 111 | [17] = "SECOND_TO", |
| 112 | }; |
| 113 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 114 | *a = ARRAY_SIZE(tco_sts_bits); |
| 115 | return tco_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 116 | } |
| 117 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 118 | const char *const *soc_std_gpe_sts_array(size_t *a) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 119 | { |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 120 | static const char *const gpe_sts_bits[] = { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 121 | [0] = "PCIE_SCI", |
| 122 | [2] = "SWGPE", |
| 123 | [3] = "PCIE_WAKE0", |
| 124 | [4] = "PUNIT", |
| 125 | [6] = "PCIE_WAKE1", |
| 126 | [7] = "PCIE_WAKE2", |
| 127 | [8] = "PCIE_WAKE3", |
| 128 | [9] = "PCI_EXP", |
| 129 | [10] = "BATLOW", |
| 130 | [11] = "CSE_PME", |
| 131 | [12] = "XDCI_PME", |
| 132 | [13] = "XHCI_PME", |
| 133 | [14] = "AVS_PME", |
| 134 | [15] = "GPIO_TIER1_SCI", |
| 135 | [16] = "SMB_WAK", |
| 136 | [17] = "SATA_PME", |
| 137 | }; |
| 138 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 139 | *a = ARRAY_SIZE(gpe_sts_bits); |
| 140 | return gpe_sts_bits; |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 141 | } |
| 142 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 143 | void soc_clear_pm_registers(uintptr_t pmc_bar) |
Duncan Laurie | 2e79009 | 2016-09-19 12:05:49 -0700 | [diff] [blame] | 144 | { |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 145 | uint32_t gen_pmcon1; |
| 146 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 147 | gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 148 | /* Clear the status bits. The RPS field is cleared on a 0 write. */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 149 | write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS); |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 150 | } |
| 151 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 152 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Hannah Williams | 01bc897 | 2016-02-04 20:13:34 -0800 | [diff] [blame] | 153 | { |
Aaron Durbin | e4d7abc | 2017-04-16 22:05:36 -0500 | [diff] [blame] | 154 | DEVTREE_CONST struct soc_intel_apollolake_config *config; |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 155 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 156 | config = config_of_soc(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 157 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 158 | /* Assign to out variable */ |
| 159 | *dw0 = config->gpe0_dw1; |
| 160 | *dw1 = config->gpe0_dw2; |
| 161 | *dw2 = config->gpe0_dw3; |
| 162 | } |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 163 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 164 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 165 | { |
| 166 | uintptr_t pmc_bar0 = read_pmc_mmio_bar(); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 167 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 168 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 169 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
| 170 | |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 171 | ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); |
| 172 | ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); |
| 173 | ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); |
| 174 | ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 175 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "prsts: %08x\n", |
| 177 | ps->prsts); |
| 178 | printk(BIOS_DEBUG, "tco_sts: %04x %04x\n", |
| 179 | ps->tco1_sts, ps->tco2_sts); |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 180 | printk(BIOS_DEBUG, |
| 181 | "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", |
| 182 | ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); |
Duncan Laurie | a673d1c | 2016-09-19 12:02:54 -0700 | [diff] [blame] | 183 | } |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 184 | |
Hannah Williams | cdecc0d | 2018-01-04 11:57:14 -0800 | [diff] [blame] | 185 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 186 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 187 | int prev_sleep_state) |
| 188 | { |
| 189 | /* WAK_STS bit will not be set when waking from G3 state */ |
| 190 | |
| 191 | if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS)) |
| 192 | prev_sleep_state = ACPI_S5; |
| 193 | return prev_sleep_state; |
| 194 | } |
| 195 | |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 196 | void enable_pm_timer_emulation(void) |
| 197 | { |
| 198 | /* ACPI PM timer emulation */ |
| 199 | msr_t msr; |
| 200 | /* |
| 201 | * The derived frequency is calculated as follows: |
| 202 | * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. |
| 203 | * Back solve the multiplier so the 3.579545MHz ACPI timer |
| 204 | * frequency is used. |
| 205 | */ |
| 206 | msr.hi = (3579545ULL << 32) / CTC_FREQ; |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 207 | /* Set PM1 timer IO port and enable */ |
Barnali Sarkar | 9e55ff6 | 2017-06-05 20:01:14 +0530 | [diff] [blame] | 208 | msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); |
Elyes HAOUAS | f212cf3 | 2018-12-18 10:24:55 +0100 | [diff] [blame] | 209 | wrmsr(MSR_EMULATE_PM_TIMER, msr); |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 210 | } |
Aaron Durbin | 3118b62 | 2017-09-15 11:48:53 -0600 | [diff] [blame] | 211 | |
| 212 | static int rtc_failed(uint32_t gen_pmcon1) |
| 213 | { |
| 214 | return !!(gen_pmcon1 & RPS); |
| 215 | } |
| 216 | |
| 217 | int soc_get_rtc_failed(void) |
| 218 | { |
| 219 | const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 220 | |
| 221 | if (!ps) { |
| 222 | printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); |
| 223 | return 1; |
| 224 | } |
| 225 | |
| 226 | return rtc_failed(ps->gen_pmcon1); |
| 227 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 228 | |
| 229 | int vbnv_cmos_failed(void) |
| 230 | { |
Furquan Shaikh | 9d07910 | 2018-02-02 15:11:29 -0800 | [diff] [blame] | 231 | uintptr_t pmc_bar = read_pmc_mmio_bar(); |
| 232 | uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); |
| 233 | int rtc_failure = rtc_failed(gen_pmcon1); |
| 234 | |
| 235 | if (rtc_failure) { |
| 236 | printk(BIOS_INFO, "RTC failed!\n"); |
| 237 | |
| 238 | /* We do not want to write 1 to clear-1 bits. Set them to 0. */ |
| 239 | gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS; |
| 240 | |
| 241 | /* RPS is write 0 to clear. */ |
| 242 | gen_pmcon1 &= ~RPS; |
| 243 | |
| 244 | write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1); |
| 245 | } |
| 246 | |
| 247 | return rtc_failure; |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 248 | } |
Eugene Myers | ebc8423 | 2020-01-21 16:46:16 -0500 | [diff] [blame] | 249 | |
| 250 | /* STM Support */ |
| 251 | uint16_t get_pmbase(void) |
| 252 | { |
| 253 | return (uint16_t) ACPI_BASE_ADDRESS; |
| 254 | } |