soc/intel: Standardize names of common MSRs
Use defined name in Intel 64 and IA-32 Architectures Software
Developer’s Manual.
Renamed MSRs are (register address, register name):
0x35 MSR_CORE_THREAD_COUNT
0x121 MSR_EMULATE_PM_TIMER
0x1f4 MSR_PRMRR_PHYS_BASE
0x1f5 MSR_PRMRR_PHYS_MASK
0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE
0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK
Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 05590bd..c36d84d 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -210,7 +210,7 @@
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
- wrmsr(MSR_EMULATE_PM_TMR, msr);
+ wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
static int rtc_failed(uint32_t gen_pmcon1)