Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 18 | #include <delay.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Kyösti Mälkki | e2227a2 | 2014-02-05 13:02:55 +0200 | [diff] [blame] | 22 | #include <device/pci_ehci.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 23 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 24 | #include <device/pci_ops.h> |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 25 | #include "pch.h" |
| 26 | |
| 27 | #ifdef __SMM__ |
| 28 | |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 29 | void usb_ehci_disable(pci_devfn_t dev) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 30 | { |
| 31 | u16 reg16; |
| 32 | u32 reg32; |
| 33 | |
| 34 | /* Set 0xDC[0]=1 */ |
| 35 | pci_or_config32(dev, 0xdc, (1 << 0)); |
| 36 | |
| 37 | /* Set D3Hot state and disable PME */ |
| 38 | reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS); |
| 39 | reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK); |
| 40 | reg16 |= PWR_CTL_SET_D3; |
| 41 | pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16); |
| 42 | |
| 43 | /* Clear memory and bus master */ |
| 44 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 45 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 46 | reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 47 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 48 | |
| 49 | /* Disable device */ |
| 50 | switch (dev) { |
| 51 | case PCH_EHCI1_DEV: |
| 52 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 53 | break; |
| 54 | case PCH_EHCI2_DEV: |
| 55 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 56 | break; |
| 57 | } |
| 58 | } |
| 59 | |
| 60 | /* Handler for EHCI controller on entry to S3/S4/S5 */ |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 61 | void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 62 | { |
| 63 | u32 reg32; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 64 | u8 *bar0_base; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 65 | u16 pwr_state; |
| 66 | u16 pci_cmd; |
| 67 | |
| 68 | /* Check if the controller is disabled or not present */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 69 | bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 70 | if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 71 | return; |
| 72 | pci_cmd = pci_read_config32(dev, PCI_COMMAND); |
| 73 | |
| 74 | switch (slp_typ) { |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 75 | case ACPI_S4: |
| 76 | case ACPI_S5: |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 77 | /* Check if controller is in D3 power state */ |
| 78 | pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS); |
| 79 | if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { |
| 80 | /* Put in D0 */ |
| 81 | u32 new_state = pwr_state & ~PWR_CTL_SET_MASK; |
| 82 | new_state |= PWR_CTL_SET_D0; |
| 83 | pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state); |
| 84 | |
| 85 | /* Make sure memory bar is set */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 86 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 87 | |
| 88 | /* Make sure memory space is enabled */ |
| 89 | pci_write_config16(dev, PCI_COMMAND, pci_cmd | |
| 90 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * If Run/Stop (bit0) is clear in USB2.0_CMD: |
| 95 | * - Clear Async Schedule Enable (bit5) and |
| 96 | * - Clear Periodic Schedule Enable (bit4) and |
| 97 | * - Set Run/Stop (bit0) |
| 98 | */ |
| 99 | reg32 = read32(bar0_base + EHCI_USB_CMD); |
| 100 | if (reg32 & EHCI_USB_CMD_RUN) { |
| 101 | reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE); |
| 102 | reg32 |= EHCI_USB_CMD_RUN; |
| 103 | write32(bar0_base + EHCI_USB_CMD, reg32); |
| 104 | } |
| 105 | |
| 106 | /* Check for Port Enabled in PORTSC(0) (RMH) */ |
| 107 | reg32 = read32(bar0_base + EHCI_PORTSC(0)); |
| 108 | if (reg32 & EHCI_PORTSC_ENABLED) { |
| 109 | /* Set suspend bit in PORTSC if not already set */ |
| 110 | if (!(reg32 & EHCI_PORTSC_SUSPEND)) { |
| 111 | reg32 |= EHCI_PORTSC_SUSPEND; |
| 112 | write32(bar0_base + EHCI_PORTSC(0), reg32); |
| 113 | } |
| 114 | |
| 115 | /* Delay 25ms !! */ |
| 116 | udelay(25 * 1000); |
| 117 | |
| 118 | /* Clear Run/Stop bit */ |
| 119 | reg32 = read32(bar0_base + EHCI_USB_CMD); |
| 120 | reg32 &= EHCI_USB_CMD_RUN; |
| 121 | write32(bar0_base + EHCI_USB_CMD, reg32); |
| 122 | } |
| 123 | |
| 124 | /* Restore state to D3 if that is what it was at the start */ |
| 125 | if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) { |
| 126 | /* Restore pci command reg */ |
| 127 | pci_write_config16(dev, PCI_COMMAND, pci_cmd); |
| 128 | |
| 129 | /* Enable D3 */ |
| 130 | pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state); |
| 131 | } |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | #else /* !__SMM__ */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 136 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 137 | static void usb_ehci_clock_gating(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | { |
| 139 | u32 reg32; |
| 140 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 141 | /* IOBP 0xE5004001[7:6] = 11b */ |
| 142 | pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 143 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 144 | /* Dx:F0:DCh[5,2,1] = 111b |
| 145 | * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ |
| 146 | reg32 = pci_read_config32(dev, 0xdc); |
| 147 | reg32 |= (1 << 5) | (1 << 2) | (1 << 1); |
| 148 | pci_write_config32(dev, 0xdc, reg32); |
| 149 | |
| 150 | /* Dx:F0:78h[1:0] = 11b */ |
| 151 | reg32 = pci_read_config32(dev, 0x78); |
| 152 | reg32 |= (1 << 1) | (1 << 0); |
| 153 | pci_write_config32(dev, 0x78, reg32); |
| 154 | } |
| 155 | |
| 156 | static void usb_ehci_init(struct device *dev) |
| 157 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 158 | printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 159 | |
| 160 | usb_ehci_clock_gating(dev); |
| 161 | |
| 162 | /* Disable Wake on Disconnect in RMH */ |
| 163 | RCBA32_OR(0x35b0, 0x00000022); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 164 | |
| 165 | printk(BIOS_DEBUG, "done.\n"); |
| 166 | } |
| 167 | |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 168 | static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, |
| 169 | unsigned int device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 170 | { |
| 171 | u8 access_cntl; |
| 172 | |
| 173 | access_cntl = pci_read_config8(dev, 0x80); |
| 174 | |
| 175 | /* Enable writes to protected registers. */ |
| 176 | pci_write_config8(dev, 0x80, access_cntl | 1); |
| 177 | |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame^] | 178 | pci_dev_set_subsystem(dev, vendor, device); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 179 | |
| 180 | /* Restore protection. */ |
| 181 | pci_write_config8(dev, 0x80, access_cntl); |
| 182 | } |
| 183 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 184 | static struct pci_operations lops_pci = { |
| 185 | .set_subsystem = &usb_ehci_set_subsystem, |
| 186 | }; |
| 187 | |
| 188 | static struct device_operations usb_ehci_ops = { |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame] | 189 | .read_resources = pci_ehci_read_resources, |
| 190 | .set_resources = pci_dev_set_resources, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 191 | .enable_resources = pci_dev_enable_resources, |
| 192 | .init = usb_ehci_init, |
| 193 | .scan_bus = 0, |
| 194 | .ops_pci = &lops_pci, |
| 195 | }; |
| 196 | |
Kyösti Mälkki | f55a542 | 2013-06-14 11:16:25 +0300 | [diff] [blame] | 197 | static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | |
| 199 | static const struct pci_driver pch_usb_ehci __pci_driver = { |
| 200 | .ops = &usb_ehci_ops, |
| 201 | .vendor = PCI_VENDOR_ID_INTEL, |
| 202 | .devices = pci_device_ids, |
| 203 | }; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 204 | |
| 205 | #endif /* !__SMM__ */ |