| Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include "pch.h" |
| 26 | #include <usbdebug.h> |
| 27 | #include <arch/io.h> |
| 28 | |
| 29 | static void usb_ehci_init(struct device *dev) |
| 30 | { |
| 31 | u32 reg32; |
| 32 | |
| 33 | /* Disable Wake on Disconnect in RMH */ |
| 34 | reg32 = RCBA32(0x35b0); |
| 35 | reg32 |= 0x22; |
| 36 | RCBA32(0x35b0) = reg32; |
| 37 | |
| 38 | printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); |
| 39 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 40 | reg32 |= PCI_COMMAND_MASTER; |
| 41 | //reg32 |= PCI_COMMAND_SERR; |
| 42 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 43 | |
| 44 | printk(BIOS_DEBUG, "done.\n"); |
| 45 | } |
| 46 | |
| 47 | static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 48 | { |
| 49 | u8 access_cntl; |
| 50 | |
| 51 | access_cntl = pci_read_config8(dev, 0x80); |
| 52 | |
| 53 | /* Enable writes to protected registers. */ |
| 54 | pci_write_config8(dev, 0x80, access_cntl | 1); |
| 55 | |
| 56 | if (!vendor || !device) { |
| 57 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 58 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 59 | } else { |
| 60 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 61 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 62 | } |
| 63 | |
| 64 | /* Restore protection. */ |
| 65 | pci_write_config8(dev, 0x80, access_cntl); |
| 66 | } |
| 67 | |
| 68 | static void usb_ehci_set_resources(struct device *dev) |
| 69 | { |
| 70 | #if CONFIG_USBDEBUG |
| 71 | struct resource *res; |
| 72 | u32 base; |
| 73 | u32 usb_debug; |
| 74 | |
| 75 | usb_debug = get_ehci_debug(); |
| 76 | set_ehci_debug(0); |
| 77 | #endif |
| 78 | pci_dev_set_resources(dev); |
| 79 | |
| 80 | #if CONFIG_USBDEBUG |
| 81 | res = find_resource(dev, 0x10); |
| 82 | set_ehci_debug(usb_debug); |
| 83 | if (!res) return; |
| 84 | base = res->base; |
| 85 | set_ehci_base(base); |
| 86 | report_resource_stored(dev, res, ""); |
| 87 | #endif |
| 88 | } |
| 89 | |
| 90 | |
| 91 | |
| 92 | static struct pci_operations lops_pci = { |
| 93 | .set_subsystem = &usb_ehci_set_subsystem, |
| 94 | }; |
| 95 | |
| 96 | static struct device_operations usb_ehci_ops = { |
| 97 | .read_resources = pci_dev_read_resources, |
| 98 | .set_resources = usb_ehci_set_resources, |
| 99 | .enable_resources = pci_dev_enable_resources, |
| 100 | .init = usb_ehci_init, |
| 101 | .scan_bus = 0, |
| 102 | .ops_pci = &lops_pci, |
| 103 | }; |
| 104 | |
| 105 | static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, |
| 106 | 0 }; |
| 107 | |
| 108 | static const struct pci_driver pch_usb_ehci __pci_driver = { |
| 109 | .ops = &usb_ehci_ops, |
| 110 | .vendor = PCI_VENDOR_ID_INTEL, |
| 111 | .devices = pci_device_ids, |
| 112 | }; |