blob: 2abc2019777a02218fccf11e6045a4aabc48f415 [file] [log] [blame]
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00001##
2## This file is part of the coreboot project.
3##
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00004##
5## This program is free software; you can redistribute it and/or modify
6## it under the terms of the GNU General Public License as published by
7## the Free Software Foundation; version 2 of the License.
8##
9## This program is distributed in the hope that it will be useful,
10## but WITHOUT ANY WARRANTY; without even the implied warranty of
11## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12## GNU General Public License for more details.
13##
Patrick Georgi0588d192009-08-12 15:00:51 +000014
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020015config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +000016 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020017
18if NORTHBRIDGE_INTEL_I945
19
20config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
21 def_bool y
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000022 select HAVE_DEBUG_RAM_SETUP
Paul Menzelea8f3b42014-09-21 12:21:36 +020023 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010024 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010025 select INTEL_GMA_SSC_ALTERNATE_REF
Patrick Rudolph46cf5c22017-04-03 19:09:45 +020026 select INTEL_EDID
Nico Huberce642f02017-05-19 15:08:21 +020027 select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
Arthur Heymansf2669322018-04-10 15:15:05 +020028 select PARALLEL_MP
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000029
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020030config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
31 def_bool n
32config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
33 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000034
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000035config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000036 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020037 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
38 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000039
Nico Huber7971582e2017-05-20 01:07:48 +020040config I945_LVDS
41 def_bool n
42 select MAINBOARD_HAS_NATIVE_VGA_INIT
43 select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
44 help
45 Selected by mainboards that use native graphics initialization
46 for the LVDS port. A linear framebuffer is only supported for
47 LVDS.
48
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020049config MMCONF_BASE_ADDRESS
50 hex
51 default 0xf0000000
52
Patrick Georgi77d66832010-10-01 08:02:45 +000053config OVERRIDE_CLOCK_DISABLE
54 bool
55 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000056 help
57 Usually system firmware turns off system memory clock
58 signals to unused SO-DIMM slots to reduce EMI and power
59 consumption.
60 However, some boards do not like unused clock signals to
61 be disabled.
62
63config MAXIMUM_SUPPORTED_FREQUENCY
64 int
65 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000066 help
67 If non-zero, this designates the maximum DDR frequency
68 the board supports, despite what the chipset should be
69 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000070
Peter Stuge751508a2012-01-27 22:17:09 +010071config CHECK_SLFRCS_ON_RESUME
72 def_bool n
73 help
74 On some boards it may be neccessary to hard reset early
75 during resume from S3 if the SLFRCS register indicates that
76 a memory channel is not guaranteed to be in self-refresh.
77 On other boards the check always creates a false positive,
78 effectively making it impossible to resume.
79
Arthur Heymansdce39272018-04-10 16:08:27 +020080config SMM_RESERVED_SIZE
81 hex
82 default 0x100000
83
Peter Stugee4bc0f62010-10-01 09:13:18 +000084endif