| Angel Pons | 47f26db | 2020-04-05 13:22:34 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Matt DeVillier | 9be3f5d | 2017-01-16 17:32:38 -0600 | [diff] [blame] | 3 | |
| 4 | #ifndef VARIANT_H |
| 5 | #define VARIANT_H |
| 6 | |
| Elyes HAOUAS | dfbe6bd | 2018-10-29 06:56:52 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
| Matt DeVillier | 9be3f5d | 2017-01-16 17:32:38 -0600 | [diff] [blame] | 9 | /* |
| 10 | * RAM_ID[2:0] are on GPIO_SSUS[39:37] |
| 11 | * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz |
| 12 | * 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz |
| 13 | * 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz |
| 14 | * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz |
| 15 | */ |
| 16 | |
| 17 | static const uint32_t dual_channel_config = |
| 18 | (1 << 2) | (1 << 3); |
| 19 | |
| 20 | #define SPD_SIZE 256 |
| 21 | #define GPIO_SSUS_37_PAD 57 |
| 22 | #define GPIO_SSUS_38_PAD 50 |
| 23 | #define GPIO_SSUS_39_PAD 58 |
| 24 | |
| 25 | #endif |