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Angel Pons47f26db2020-04-05 13:22:34 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06003
4#ifndef VARIANT_H
5#define VARIANT_H
6
Elyes HAOUASdfbe6bd2018-10-29 06:56:52 +01007#include <stdint.h>
8
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06009/*
10 * RAM_ID[2:0] are on GPIO_SSUS[39:37]
11 * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
12 * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
13 * 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
14 * 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
15 * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
16 * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
17 * 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
18 * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
19 */
20
21static const uint32_t dual_channel_config =
22 (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
23
24#define SPD_SIZE 256
25#define GPIO_SSUS_37_PAD 57
26#define GPIO_SSUS_38_PAD 50
27#define GPIO_SSUS_39_PAD 58
28
29#endif