blob: 7f058d7ccb1703141484b9d5aba2f884492822f7 [file] [log] [blame]
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef VARIANT_H
15#define VARIANT_H
16
17/*
18 * RAM_ID[2:0] are on GPIO_SSUS[39:37]
19 * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
20 * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
21 * 0b010 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
22 * 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
23 * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
24 * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
25 * 0b110 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
26 * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
27 */
28
29static const uint32_t dual_channel_config =
30 (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
31
32#define SPD_SIZE 256
33#define GPIO_SSUS_37_PAD 57
34#define GPIO_SSUS_38_PAD 50
35#define GPIO_SSUS_39_PAD 58
36
37#endif