Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 2 | |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 3 | #include <assert.h> |
| 4 | #include <commonlib/sort.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 6 | #include <delay.h> |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 7 | #include <device/device.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 8 | #include <device/pci.h> |
Jonathan Zhang | 665d870 | 2023-01-24 11:18:15 -0800 | [diff] [blame] | 9 | #include <intelblocks/cfg.h> |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 10 | #include <intelblocks/cpulib.h> |
Jonathan Zhang | 665d870 | 2023-01-24 11:18:15 -0800 | [diff] [blame] | 11 | #include <intelpch/lockdown.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
Marc Jones | 53b465d | 2020-10-15 15:16:45 -0600 | [diff] [blame] | 13 | #include <soc/msr.h> |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 14 | #include <soc/soc_util.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 15 | #include <soc/util.h> |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 16 | #include <timer.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 17 | |
Jonathan Zhang | 665d870 | 2023-01-24 11:18:15 -0800 | [diff] [blame] | 18 | void lock_pam0123(void) |
| 19 | { |
| 20 | if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) |
| 21 | return; |
| 22 | |
| 23 | /* section 16.3.19 of Intel doc. #612246 */ |
| 24 | uint32_t pam0123_lock = 0x33333331; |
| 25 | uint32_t bus1 = get_socket_ubox_busno(0); |
| 26 | |
| 27 | pci_s_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), |
| 28 | SAD_ALL_PAM0123_CSR, pam0123_lock); |
| 29 | } |
| 30 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 31 | void unlock_pam_regions(void) |
| 32 | { |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 33 | uint32_t pam0123_unlock_dram = 0x33333330; |
| 34 | uint32_t pam456_unlock_dram = 0x00333333; |
Jonathan Zhang | ca520a7 | 2023-01-23 18:14:53 -0800 | [diff] [blame] | 35 | uint32_t bus1 = get_socket_ubox_busno(0); |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 36 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 37 | pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), |
| 38 | SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); |
| 39 | pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), |
| 40 | SAD_ALL_PAM456_CSR, pam456_unlock_dram); |
| 41 | |
| 42 | uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, |
| 43 | SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); |
| 44 | uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, |
| 45 | SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); |
| 46 | printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", |
| 47 | __FILE__, __func__, reg1, reg2); |
| 48 | } |
| 49 | |
Marc Jones | 53b465d | 2020-10-15 15:16:45 -0600 | [diff] [blame] | 50 | msr_t read_msr_ppin(void) |
| 51 | { |
| 52 | msr_t ppin = {0}; |
| 53 | msr_t msr; |
| 54 | |
| 55 | /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ |
| 56 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 57 | if ((msr.lo & MSR_PPIN_CAP) == 0) { |
| 58 | printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); |
| 59 | return ppin; |
| 60 | } |
| 61 | |
| 62 | /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ |
| 63 | msr = rdmsr(MSR_PPIN_CTL); |
| 64 | if (msr.lo & MSR_PPIN_CTL_LOCK) { |
| 65 | printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); |
| 66 | return ppin; |
| 67 | } |
| 68 | |
| 69 | if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { |
| 70 | /* Set MSR_PPIN_CTL ENABLE to 1 */ |
| 71 | msr.lo |= MSR_PPIN_CTL_ENABLE; |
| 72 | wrmsr(MSR_PPIN_CTL, msr); |
| 73 | } |
| 74 | ppin = rdmsr(MSR_PPIN); |
Marc Jones | 53b465d | 2020-10-15 15:16:45 -0600 | [diff] [blame] | 75 | return ppin; |
| 76 | } |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 77 | |
Angel Pons | d453da2 | 2021-11-03 16:10:56 +0100 | [diff] [blame] | 78 | static unsigned int get_threads_per_package(void) |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 79 | { |
| 80 | unsigned int core_count, thread_count; |
| 81 | cpu_read_topology(&core_count, &thread_count); |
| 82 | return thread_count; |
| 83 | } |
| 84 | |
| 85 | int get_platform_thread_count(void) |
| 86 | { |
| 87 | return soc_get_num_cpus() * get_threads_per_package(); |
| 88 | } |
| 89 | |
| 90 | const IIO_UDS *get_iio_uds(void) |
| 91 | { |
| 92 | size_t hob_size; |
Arthur Heymans | 12985c1 | 2020-11-06 11:45:41 +0100 | [diff] [blame] | 93 | static const IIO_UDS *hob; |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 94 | const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 95 | |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 96 | if (hob) |
Arthur Heymans | 12985c1 | 2020-11-06 11:45:41 +0100 | [diff] [blame] | 97 | return hob; |
| 98 | |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 99 | hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 100 | assert(hob && hob_size != 0); |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 101 | return hob; |
| 102 | } |
| 103 | |
Patrick Rudolph | b096d62 | 2023-07-14 17:18:18 +0200 | [diff] [blame] | 104 | /* |
| 105 | * Returns true if the CPU in the specified socket was found |
| 106 | * during QPI init, false otherwise. |
| 107 | */ |
| 108 | bool soc_cpu_is_enabled(const size_t idx) |
| 109 | { |
| 110 | const IIO_UDS *hob = get_iio_uds(); |
| 111 | assert(idx < CONFIG_MAX_SOCKET); |
| 112 | |
| 113 | return hob->PlatformData.IIO_resource[idx].Valid; |
| 114 | } |
| 115 | |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 116 | unsigned int soc_get_num_cpus(void) |
| 117 | { |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 118 | return get_iio_uds()->SystemStatus.numCpus; |
| 119 | } |
| 120 | |
| 121 | #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 122 | /* return true if command timed out else false */ |
| 123 | static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, |
| 124 | uint32_t target) |
| 125 | { |
| 126 | const uint32_t max_delay = 5000; /* 5 seconds max */ |
| 127 | const uint32_t step_delay = 50; /* 50 us */ |
| 128 | struct stopwatch sw; |
| 129 | |
| 130 | stopwatch_init_msecs_expire(&sw, max_delay); |
| 131 | while ((pci_s_read_config32(dev, reg) & mask) != target) { |
| 132 | udelay(step_delay); |
| 133 | if (stopwatch_expired(&sw)) { |
| 134 | printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, " |
| 135 | "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); |
| 136 | return true; /* timedout */ |
| 137 | } |
| 138 | } |
| 139 | return false; /* successful */ |
| 140 | } |
| 141 | |
| 142 | /* return true if command timed out else false */ |
| 143 | static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) |
| 144 | { |
| 145 | /* verify bios is not in busy state */ |
| 146 | if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) |
| 147 | return true; /* timed out */ |
| 148 | |
| 149 | /* write data to data register */ |
| 150 | printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__, |
| 151 | PCU_CR1_BIOS_MB_DATA_REG, data); |
| 152 | pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); |
| 153 | |
| 154 | /* write the command */ |
| 155 | printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__, |
| 156 | PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK); |
| 157 | pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, |
| 158 | command | BIOS_MB_RUN_BUSY_MASK); |
| 159 | |
| 160 | /* wait for completion or time out*/ |
| 161 | return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, |
| 162 | BIOS_MB_RUN_BUSY_MASK, 0); |
| 163 | } |
| 164 | |
| 165 | /* return true if command timed out else false */ |
| 166 | static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, |
| 167 | uint32_t pcode_init_mask, uint32_t val) |
| 168 | { |
Jonathan Zhang | ca520a7 | 2023-01-23 18:14:53 -0800 | [diff] [blame] | 169 | const uint32_t bus = get_socket_ubox_busno(socket); |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 170 | const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); |
| 171 | |
| 172 | uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 173 | reg &= (uint32_t)~rst_cpl_mask; |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 174 | reg |= val; |
| 175 | |
| 176 | /* update BIOS RESET completion bit */ |
| 177 | pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); |
| 178 | |
| 179 | /* wait for PCU ack */ |
| 180 | return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, |
| 181 | pcode_init_mask); |
| 182 | } |
| 183 | |
| 184 | static void set_bios_init_completion_for_package(uint32_t socket) |
| 185 | { |
| 186 | uint32_t data; |
| 187 | bool timedout; |
Jonathan Zhang | ca520a7 | 2023-01-23 18:14:53 -0800 | [diff] [blame] | 188 | const uint32_t bus = get_socket_ubox_busno(socket); |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 189 | const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); |
| 190 | |
| 191 | /* read PCU config */ |
| 192 | timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); |
| 193 | if (timedout) { |
| 194 | /* 2nd try */ |
| 195 | timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); |
| 196 | if (timedout) |
| 197 | die("BIOS PCU Misc Config Read timed out.\n"); |
| 198 | |
| 199 | /* Since the 1st try failed, we need to make sure PCU is in stable state */ |
| 200 | data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); |
| 201 | printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n", |
| 202 | __func__, PCU_CR1_BIOS_MB_DATA_REG, data); |
| 203 | timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); |
| 204 | if (timedout) |
| 205 | die("BIOS PCU Misc Config Write timed out.\n"); |
| 206 | } |
| 207 | |
| 208 | /* update RST_CPL3, PCODE_INIT_DONE3 */ |
| 209 | timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, |
| 210 | PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); |
| 211 | if (timedout) |
| 212 | die("BIOS RESET CPL3 timed out.\n"); |
| 213 | |
Marc Jones | 4fad28f | 2021-04-01 14:47:52 -0600 | [diff] [blame] | 214 | /* Set PMAX_LOCK - must be set before RESET CPL4 */ |
Jonathan Zhang | ffc5a1c | 2023-01-23 16:33:03 -0800 | [diff] [blame] | 215 | data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); |
| 216 | data |= PMAX_LOCK; |
| 217 | pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); |
Marc Jones | 4fad28f | 2021-04-01 14:47:52 -0600 | [diff] [blame] | 218 | |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 219 | /* update RST_CPL4, PCODE_INIT_DONE4 */ |
| 220 | timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, |
| 221 | PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); |
| 222 | if (timedout) |
| 223 | die("BIOS RESET CPL4 timed out.\n"); |
| 224 | |
| 225 | /* set CSR_DESIRED_CORES_CFG2 lock bit */ |
| 226 | data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); |
| 227 | data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; |
| 228 | printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", |
| 229 | __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); |
| 230 | pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); |
| 231 | } |
| 232 | |
| 233 | void set_bios_init_completion(void) |
| 234 | { |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 235 | uint32_t sbsp_socket_id = 0; |
| 236 | |
| 237 | /* |
| 238 | * According to the BIOS Writer's Guide, the SBSP must be the last socket |
| 239 | * to receive the BIOS init completion message. So, we send it to all non-SBSP |
| 240 | * sockets first. |
| 241 | */ |
Patrick Rudolph | ac02857 | 2023-07-14 17:44:33 +0200 | [diff] [blame] | 242 | for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { |
| 243 | if (!soc_cpu_is_enabled(socket)) |
| 244 | continue; |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 245 | if (socket == sbsp_socket_id) |
| 246 | continue; |
| 247 | set_bios_init_completion_for_package(socket); |
| 248 | } |
| 249 | |
| 250 | /* And finally, take care of the SBSP */ |
| 251 | set_bios_init_completion_for_package(sbsp_socket_id); |
| 252 | } |
Marc Jones | 18960ce | 2020-11-02 12:41:12 -0700 | [diff] [blame] | 253 | #endif |