Patrick Georgi | 11f0079 | 2020-03-04 15:10:45 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | 425b61e | 2015-03-15 04:29:35 +0100 | [diff] [blame] | 2 | |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 3 | config ARCH_X86 |
| 4 | bool |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 5 | select PCI |
Kyösti Mälkki | ec151f0 | 2018-06-03 22:48:51 +0300 | [diff] [blame] | 6 | select RELOCATABLE_MODULES |
Stefan Reinauer | a48ca84 | 2015-04-04 01:58:28 +0200 | [diff] [blame] | 7 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 8 | # stage selectors for x86 |
| 9 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 10 | config ARCH_BOOTBLOCK_X86_32 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 11 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 12 | select ARCH_X86 |
| 13 | |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 14 | config ARCH_VERSTAGE_X86_32 |
| 15 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 16 | select ARCH_X86 |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 17 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 18 | config ARCH_ROMSTAGE_X86_32 |
| 19 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 20 | select ARCH_X86 |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 21 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 22 | config ARCH_POSTCAR_X86_32 |
| 23 | bool |
| 24 | default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE |
| 25 | |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 26 | config ARCH_RAMSTAGE_X86_32 |
| 27 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 28 | select ARCH_X86 |
Gabe Black | 5fbfc91 | 2013-07-07 13:52:37 -0700 | [diff] [blame] | 29 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 30 | # stage selectors for x64 |
| 31 | |
| 32 | config ARCH_BOOTBLOCK_X86_64 |
| 33 | bool |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 34 | select ARCH_X86 |
| 35 | |
| 36 | config ARCH_VERSTAGE_X86_64 |
| 37 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 38 | select ARCH_X86 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 39 | |
| 40 | config ARCH_ROMSTAGE_X86_64 |
| 41 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 42 | select ARCH_X86 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 43 | |
Patrick Georgi | 29eeece | 2018-10-31 14:24:47 +0100 | [diff] [blame] | 44 | config ARCH_POSTCAR_X86_64 |
| 45 | bool |
| 46 | default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE |
| 47 | |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 48 | config ARCH_RAMSTAGE_X86_64 |
| 49 | bool |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 50 | select ARCH_X86 |
| 51 | |
| 52 | if ARCH_X86 |
Stefan Reinauer | 6867120 | 2015-03-15 04:34:03 +0100 | [diff] [blame] | 53 | |
Patrick Rudolph | b1ef725 | 2019-09-28 17:44:01 +0200 | [diff] [blame] | 54 | config ARCH_X86_64_PGTBL_LOC |
| 55 | hex "x86_64 page table location in CBFS" |
| 56 | depends on ARCH_BOOTBLOCK_X86_64 |
| 57 | default 0xfffea000 |
| 58 | help |
| 59 | The position where to place pagetables. Needs to be known at |
| 60 | compile time. Must not overlap other files in CBFS. |
| 61 | |
Martin Roth | 0cd9ff8 | 2016-02-01 17:33:37 -0700 | [diff] [blame] | 62 | config USE_MARCH_586 |
| 63 | def_bool n |
| 64 | help |
| 65 | Allow a platform or processor to select to be compiled using |
| 66 | the '-march=i586' option instead of the typical '-march=i686' |
| 67 | |
Uwe Hermann | 168b11b | 2009-10-07 16:15:40 +0000 | [diff] [blame] | 68 | # This is an SMP option. It relates to starting up APs. |
| 69 | # It is usually set in mainboard/*/Kconfig. |
| 70 | # TODO: Improve description. |
Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 71 | config AP_IN_SIPI_WAIT |
| 72 | bool |
| 73 | default n |
Stefan Reinauer | 2a6f390 | 2012-10-15 13:38:09 -0700 | [diff] [blame] | 74 | depends on ARCH_X86 && SMP |
Ronald G. Minnich | 6ed39d9 | 2009-08-29 02:59:35 +0000 | [diff] [blame] | 75 | |
Marshall Dawson | 67910db | 2019-11-01 17:30:05 -0600 | [diff] [blame] | 76 | config X86_RESET_VECTOR |
| 77 | hex |
| 78 | depends on ARCH_X86 |
| 79 | default 0xfffffff0 |
| 80 | help |
| 81 | Specify the location of the x86 reset vector. In traditional devices |
| 82 | this must match the architectural reset vector to produce a bootable |
| 83 | image. Nontraditional designs may use this to position the reset |
| 84 | vector into its desired location. |
| 85 | |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 86 | config RESET_VECTOR_IN_RAM |
| 87 | bool |
| 88 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 89 | select NO_XIP_EARLY_STAGES |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 90 | help |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 91 | Select this option if the x86 processor's reset vector is in |
| 92 | preinitialized DRAM instead of the traditional 0xfffffff0 location. |
Martin Roth | 8418fd4 | 2019-04-22 16:26:23 -0600 | [diff] [blame] | 93 | |
Kyösti Mälkki | f8c7c23 | 2012-04-06 04:03:50 +0300 | [diff] [blame] | 94 | # Aligns 16bit entry code in bootblock so that hyper-threading CPUs |
| 95 | # can boot AP CPUs to enable their shared caches. |
| 96 | config SIPI_VECTOR_IN_ROM |
| 97 | bool |
| 98 | default n |
| 99 | depends on ARCH_X86 |
| 100 | |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 101 | # Set the rambase for systems that still need it, only 5 chipsets as of |
| 102 | # Sep 2018. This value was 0x100000, chosen to match the entry point |
| 103 | # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense |
| 104 | # for as long as we need it; with luck, that won't be much longer. |
| 105 | # In the long term, both RAMBASE and RAMTOP should be removed. |
| 106 | # This value leaves more than 1 MiB which is required for fam10 |
| 107 | # and broadwell_de. |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 108 | config RAMBASE |
| 109 | hex |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 110 | default 0xe00000 |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 111 | |
Kyösti Mälkki | bec853e | 2016-06-15 02:25:00 +0300 | [diff] [blame] | 112 | config RAMTOP |
| 113 | hex |
Ronald G. Minnich | 83bd46e | 2018-09-16 09:59:54 -0700 | [diff] [blame] | 114 | default 0x1000000 |
Kyösti Mälkki | bec853e | 2016-06-15 02:25:00 +0300 | [diff] [blame] | 115 | depends on ARCH_X86 |
| 116 | |
Alexandru Gagniuc | 6a62231 | 2015-10-27 10:27:30 -0700 | [diff] [blame] | 117 | # Traditionally BIOS region on SPI flash boot media was memory mapped right below |
| 118 | # 4G and it was the last region in the IFD. This way translation between CPU |
| 119 | # address space to flash address was trivial. However some IFDs on newer SoCs |
| 120 | # have BIOS region sandwiched between descriptor and other regions. Turning off |
| 121 | # this option enables soc code to provide custom mmap_boot.c which can be used to |
| 122 | # implement complex translation. |
| 123 | config X86_TOP4G_BOOTMEDIA_MAP |
| 124 | bool |
| 125 | default y |
| 126 | |
Ronald G. Minnich | b5e777c | 2013-07-22 20:17:18 +0200 | [diff] [blame] | 127 | # This is something you almost certainly don't want to mess with. |
| 128 | # How many SIPIs do we send when starting up APs and cores? |
| 129 | # The answer in 2000 or so was '2'. Nowadays, on many systems, |
| 130 | # it is 1. Set a safe default here, and you can override it |
| 131 | # on reasonable platforms. |
| 132 | config NUM_IPI_STARTS |
| 133 | int |
| 134 | default 2 |
| 135 | |
Kyösti Mälkki | a7dd645 | 2017-04-19 07:37:38 +0300 | [diff] [blame] | 136 | config CBMEM_TOP_BACKUP |
| 137 | def_bool n |
| 138 | help |
| 139 | Platform implements non-volatile storage to cache cbmem_top() |
| 140 | over stage transitions and optionally also over S3 suspend. |
| 141 | |
Naresh G Solanki | 04bb480 | 2016-12-13 21:16:46 +0530 | [diff] [blame] | 142 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 143 | hex |
| 144 | default 0xc00 |
| 145 | help |
| 146 | Increase this value if preram cbmem console is getting truncated |
| 147 | |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 148 | config PC80_SYSTEM |
| 149 | bool |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 150 | default y if ARCH_X86 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 151 | |
Lee Leahy | fdc8c8b | 2016-06-07 08:45:17 -0700 | [diff] [blame] | 152 | config BOOTBLOCK_DEBUG_SPINLOOP |
| 153 | bool |
| 154 | default n |
| 155 | help |
| 156 | Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait |
| 157 | for a JTAG debugger to break into the execution sequence. |
| 158 | |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 159 | config HAVE_CMOS_DEFAULT |
| 160 | def_bool n |
Martin Roth | f76303e | 2016-11-16 15:45:22 -0700 | [diff] [blame] | 161 | depends on HAVE_OPTION_TABLE |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 162 | |
| 163 | config CMOS_DEFAULT_FILE |
| 164 | string |
Denis 'GNUtoo' Carikli | 29a4355 | 2013-05-28 13:46:12 +0200 | [diff] [blame] | 165 | default "src/mainboard/$(MAINBOARDDIR)/cmos.default" |
Patrick Georgi | a865b17 | 2011-01-14 07:40:24 +0000 | [diff] [blame] | 166 | depends on HAVE_CMOS_DEFAULT |
| 167 | |
Patrick Georgi | d4d5e4d | 2012-03-16 19:28:15 +0100 | [diff] [blame] | 168 | config IOAPIC_INTERRUPTS_ON_FSB |
| 169 | bool |
| 170 | default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 171 | |
| 172 | config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS |
| 173 | bool |
| 174 | default n |
| 175 | |
Kyösti Mälkki | b433d26 | 2018-05-24 09:56:11 +0300 | [diff] [blame] | 176 | config HPET_ADDRESS_OVERRIDE |
| 177 | def_bool n |
| 178 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 179 | config HPET_ADDRESS |
| 180 | hex |
| 181 | default 0xfed00000 if !HPET_ADDRESS_OVERRIDE |
| 182 | |
Stefan Reinauer | 8483344 | 2012-11-13 15:04:12 -0800 | [diff] [blame] | 183 | config ID_SECTION_OFFSET |
| 184 | hex |
| 185 | default 0x80 |
Patrick Georgi | c32a52c | 2015-06-22 21:10:34 +0200 | [diff] [blame] | 186 | |
Arthur Heymans | c05b1a6 | 2019-11-22 21:01:30 +0100 | [diff] [blame] | 187 | # 64KiB default bootblock size |
Aaron Durbin | 65ac3d8 | 2016-02-11 14:36:19 -0600 | [diff] [blame] | 188 | config C_ENV_BOOTBLOCK_SIZE |
| 189 | hex |
| 190 | default 0x10000 |
Andrey Petrov | ccd300b | 2016-02-28 22:04:51 -0800 | [diff] [blame] | 191 | |
| 192 | # Default address romstage is to be linked at |
| 193 | config ROMSTAGE_ADDR |
| 194 | hex |
| 195 | default 0x2000000 |
| 196 | |
| 197 | # Default address verstage is to be linked at |
| 198 | config VERSTAGE_ADDR |
| 199 | hex |
| 200 | default 0x2000000 |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 201 | |
| 202 | # Use the post CAR infrastructure for tearing down cache-as-ram |
Elyes HAOUAS | 777ea89 | 2016-07-29 07:40:41 +0200 | [diff] [blame] | 203 | # from a program loaded in RAM and subsequently loading ramstage. |
Aaron Durbin | 7f8afe0 | 2016-03-18 12:21:23 -0500 | [diff] [blame] | 204 | config POSTCAR_STAGE |
Kyösti Mälkki | 0f5e01a | 2019-08-09 07:11:07 +0300 | [diff] [blame] | 205 | def_bool y |
| 206 | depends on ARCH_X86 |
Felix Held | ca928c6 | 2020-04-04 01:47:37 +0200 | [diff] [blame] | 207 | depends on !RESET_VECTOR_IN_RAM |
Lee Leahy | d131ea3 | 2016-06-08 13:40:08 -0700 | [diff] [blame] | 208 | |
| 209 | config VERSTAGE_DEBUG_SPINLOOP |
| 210 | bool |
| 211 | default n |
| 212 | help |
| 213 | Add a spin (JMP .) in assembly_entry.S during early verstage to wait |
| 214 | for a JTAG debugger to break into the execution sequence. |
| 215 | |
| 216 | config ROMSTAGE_DEBUG_SPINLOOP |
| 217 | bool |
| 218 | default n |
| 219 | help |
| 220 | Add a spin (JMP .) in assembly_entry.S during early romstage to wait |
| 221 | for a JTAG debugger to break into the execution sequence. |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 222 | |
| 223 | choice |
| 224 | prompt "Bootblock behaviour" |
| 225 | default BOOTBLOCK_SIMPLE |
Kyösti Mälkki | b8d575c | 2019-12-16 16:00:49 +0200 | [diff] [blame] | 226 | depends on !VBOOT |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 227 | |
| 228 | config BOOTBLOCK_SIMPLE |
| 229 | bool "Always load fallback" |
| 230 | |
| 231 | config BOOTBLOCK_NORMAL |
Arthur Heymans | 6f75154 | 2019-06-08 11:28:52 +0200 | [diff] [blame] | 232 | select CONFIGURABLE_CBFS_PREFIX |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 233 | bool "Switch to normal if CMOS says so" |
| 234 | |
| 235 | endchoice |
| 236 | |
Martin Roth | 408fda7 | 2016-12-15 16:04:55 -0700 | [diff] [blame] | 237 | config SKIP_MAX_REBOOT_CNT_CLEAR |
| 238 | bool "Do not clear reboot count after successful boot" |
| 239 | depends on BOOTBLOCK_NORMAL |
| 240 | help |
| 241 | Do not clear the reboot count immediately after successful boot. |
| 242 | Set to allow the payload to control normal/fallback image recovery. |
| 243 | Note that it is the responsibility of the payload to reset the |
Paul Menzel | b949902 | 2019-01-08 16:21:31 +0100 | [diff] [blame] | 244 | normal boot bit to 1 after each successful boot. |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 245 | |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 246 | config ACPI_BERT |
Nico Huber | 9df72e0 | 2018-11-24 18:25:50 +0100 | [diff] [blame] | 247 | bool |
Marc Jones | 7a2d4ea | 2017-08-25 18:54:23 -0600 | [diff] [blame] | 248 | depends on HAVE_ACPI_TABLES |
| 249 | help |
Furquan Shaikh | bf4b7b0 | 2020-04-30 18:08:16 -0700 | [diff] [blame] | 250 | Build an ACPI Boot Error Record Table. |
Aaron Durbin | f49ddb6 | 2018-01-24 17:35:58 -0700 | [diff] [blame] | 251 | |
| 252 | config COLLECT_TIMESTAMPS_NO_TSC |
| 253 | bool |
| 254 | default n |
| 255 | depends on COLLECT_TIMESTAMPS |
| 256 | help |
| 257 | Use a non-TSC platform-dependent source for timestamps. |
| 258 | |
| 259 | config COLLECT_TIMESTAMPS_TSC |
| 260 | bool |
| 261 | default y if !COLLECT_TIMESTAMPS_NO_TSC |
| 262 | default n |
| 263 | depends on COLLECT_TIMESTAMPS |
| 264 | help |
| 265 | Use the TSC as the timestamp source. |
Aaron Durbin | 0f35af8f | 2018-04-18 01:00:27 -0600 | [diff] [blame] | 266 | |
| 267 | config PAGING_IN_CACHE_AS_RAM |
| 268 | bool |
| 269 | default n |
| 270 | depends on ARCH_X86 |
| 271 | help |
| 272 | Chipsets scan select this option to preallocate area in cache-as-ram |
| 273 | for storing paging data structures. PAE paging is currently the |
| 274 | only thing being supported. |
| 275 | |
| 276 | config NUM_CAR_PAGE_TABLE_PAGES |
| 277 | int |
| 278 | default 5 |
| 279 | depends on PAGING_IN_CACHE_AS_RAM |
| 280 | help |
| 281 | The number of 4KiB pages that should be pre-allocated for page tables. |
Aaron Durbin | 4b032e4 | 2018-04-20 01:39:30 -0600 | [diff] [blame] | 282 | |
| 283 | # Provide the interrupt handlers to every stage. Not all |
| 284 | # stages may take advantage. |
| 285 | config IDT_IN_EVERY_STAGE |
| 286 | bool |
| 287 | default n |
| 288 | depends on ARCH_X86 |
Nico Huber | 33fcaf9 | 2018-10-10 22:44:20 +0200 | [diff] [blame] | 289 | |
| 290 | config HAVE_CF9_RESET |
| 291 | bool |
| 292 | |
| 293 | config HAVE_CF9_RESET_PREPARE |
| 294 | bool |
| 295 | depends on HAVE_CF9_RESET |
Kyösti Mälkki | b72b5d9 | 2019-07-04 21:08:17 +0300 | [diff] [blame] | 296 | |
| 297 | config PIRQ_ROUTE |
| 298 | bool |
| 299 | default n |
| 300 | |
| 301 | config MAX_PIRQ_LINKS |
| 302 | int |
| 303 | default 4 |
| 304 | depends on PIRQ_ROUTE |
| 305 | help |
| 306 | This variable specifies the number of PIRQ interrupt links which are |
| 307 | routable. On most chipsets, this is 4, INTA through INTD. Some |
| 308 | chipsets offer more than four links, commonly up to INTH. They may |
| 309 | also have a separate link for ATA or IOAPIC interrupts. When the PIRQ |
| 310 | table specifies links greater than 4, pirq_route_irqs will not |
| 311 | function properly, unless this variable is correctly set. |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 312 | |
Duncan Laurie | f02bf35 | 2020-03-17 18:32:54 -0700 | [diff] [blame] | 313 | config MAX_ACPI_TABLE_SIZE_KB |
| 314 | int |
| 315 | default 144 |
| 316 | help |
| 317 | Set the maximum size of all ACPI tables in KiB. |
| 318 | |
Arthur Heymans | b86e96a | 2019-02-10 17:00:56 +0100 | [diff] [blame] | 319 | endif |