Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 18 | /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 19 | |
| 20 | #include <stdint.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 21 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 22 | #include <cf9_reset.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 24 | #include <device/pci_def.h> |
Edward O'Callaghan | cea4557 | 2014-11-19 12:08:24 +1100 | [diff] [blame] | 25 | #include <cpu/intel/romstage.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 26 | #include <cpu/x86/lapic.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 27 | #include <console/console.h> |
| 28 | #include <cpu/x86/bist.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <northbridge/intel/i945/i945.h> |
| 30 | #include <northbridge/intel/i945/raminit.h> |
| 31 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 32 | #include <southbridge/intel/common/pmclib.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 33 | |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 34 | static void ich7_enable_lpc(void) |
| 35 | { |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 36 | /* Enable Serial IRQ */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 37 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 38 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 39 | /* I/O Decode Ranges |
| 40 | * X60: 0x0210 == 00000010 00010000 |
| 41 | * Macbook21: 0x0010 == 00000000 00010000 |
| 42 | * Bit 9:8 LPT Decode Range. This field determines which range to |
| 43 | * decode for the LPT Port. |
| 44 | * 00 = 378h - 37Fh and 778h - 77Fh |
| 45 | * 10 = 3BCh - 3BEh and 7BCh - 7BEh |
| 46 | */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 47 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 48 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 49 | /* LPC_EN--LPC I/F Enables Register |
| 50 | * X60: 0x1f0d == 00011111 00001101 |
| 51 | * Macbook21: 0x3807 == 00111000 00000111 |
| 52 | * Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. |
| 53 | * 0 = Disable. |
| 54 | * 1 = Enables the decoding of the I/O locations 4Eh and 4Fh |
| 55 | * to the LPC interface. This range is used for a |
| 56 | * microcontroller. |
| 57 | * Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. |
| 58 | * 0 = Disable. |
| 59 | * 1 = Enables the decoding of the I/O locations 2Eh and 2Fh |
| 60 | * to the LPC interface. This range is used for |
| 61 | * Super I/O devices. |
| 62 | * Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. |
| 63 | * 0 = Disable. |
| 64 | * 1 = Enables the decoding of the I/O locations 62h and 66h |
| 65 | * to the LPC interface. This range is used for a |
| 66 | * microcontroller. |
| 67 | * Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. |
| 68 | * 0 = Disable. |
| 69 | * 1 = Enables the decoding of the I/O locations 60h and 64h |
| 70 | * to the LPC interface. This range is used for a |
| 71 | * microcontroller. |
| 72 | * Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable |
| 73 | * 0 = Disable. |
| 74 | * 1 = Enables the decoding of the I/O locations 208h to 20Fh |
| 75 | * to the LPC interface. This range is used for a gameport. |
| 76 | * Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable |
| 77 | * 0 = Disable. |
| 78 | * 1 = Enables the decoding of the I/O locations 200h to 207h |
| 79 | * to the LPC interface. This range is used for a gameport. |
| 80 | * Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable |
| 81 | * 0 = Disable. |
| 82 | * 1 = Enables the decoding of the FDD range to the LPC |
| 83 | * interface. This range is selected in the LPC_FDD/LPT |
| 84 | * Decode Range Register (D31:F0:80h, bit 12). |
| 85 | * Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable |
| 86 | * 0 = Disable. |
| 87 | * 1 = Enables the decoding of the LPT range to the LPC |
| 88 | * interface. This range is selected in the LPC_FDD/LPT |
| 89 | * Decode Range Register (D31:F0:80h, bit 9:8). |
| 90 | * Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable |
| 91 | * 0 = Disable. |
| 92 | * 1 = Enables the decoding of the COMB range to the LPC |
| 93 | * interface. This range is selected in the LPC_COM Decode |
| 94 | * Range Register (D31:F0:80h, bits 6:4). |
| 95 | * Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable |
| 96 | * 0 = Disable. |
| 97 | * 1 = Enables the decoding of the COMA range to the LPC |
| 98 | * interface. This range is selected in the LPC_COM Decode |
| 99 | * Range Register (D31:F0:80h, bits 3:2). |
| 100 | */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 101 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN |
| 102 | | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN |
| 103 | | COMA_LPC_EN); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 104 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 105 | /* GEN1_DEC, LPC Interface Generic Decode Range 1 |
| 106 | * X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 |
| 107 | * Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 |
| 108 | * Bit 31:24 Reserved. |
| 109 | * Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any |
| 110 | * bit position indicates that any value in the corresponding |
| 111 | * address bit in a received cycle will be treated as a |
| 112 | * match. The corresponding bit in the Address field, below, |
| 113 | * is ignored. The mask is only provided for the lower 6 bits |
| 114 | * of the DWord address, allowing for decoding blocks up to |
| 115 | * 256 bytes in size. |
| 116 | * Bit 17:16 Reserved. |
| 117 | * Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This |
| 118 | * address is aligned on a 128-byte boundary, and must have |
| 119 | * address lines 31:16 as 0. NOTE: The Intel ICH7 does not |
| 120 | * provide decode down to the word or byte level. |
| 121 | * Bit 1 Reserved. |
| 122 | * Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. |
| 123 | * 0 = Disable. |
| 124 | * 1 = Enable the GEN1 I/O range to be forwarded to the LPC |
| 125 | * I/F |
| 126 | */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 127 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 128 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 129 | /* GEN2_DEC, LPC Interface Generic Decode Range 2 |
| 130 | * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 |
| 131 | * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 |
| 132 | */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 133 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 134 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 135 | /* GEN4_DEC, LPC Interface Generic Decode Range 4 |
| 136 | * X60: 0x0000 0x0000 |
| 137 | * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 |
| 138 | */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 139 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void rcba_config(void) |
| 143 | { |
| 144 | /* V0CTL Virtual Channel 0 Resource Control */ |
| 145 | RCBA32(0x0014) = 0x80000001; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 146 | |
| 147 | /* Device 1f interrupt pin register */ |
| 148 | RCBA32(0x3100) = 0x00042210; |
| 149 | RCBA32(0x3108) = 0x10004321; |
| 150 | |
| 151 | /* PCIe Interrupts */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 152 | RCBA32(D28IP) = 0x00214321; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 153 | /* HD Audio Interrupt */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 154 | RCBA32(D27IP) = 0x00000001; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 155 | |
| 156 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 157 | RCBA16(D31IR) = 0x0232; |
| 158 | RCBA16(D30IR) = 0x3246; |
| 159 | RCBA16(D29IR) = 0x0235; |
| 160 | RCBA16(D28IR) = 0x3201; |
| 161 | RCBA16(D27IR) = 0x3216; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 162 | |
| 163 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 164 | RCBA8(OIC) = 0x03; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 165 | |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 166 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 167 | RCBA32(FD) |= FD_INTLAN; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 168 | |
| 169 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 170 | |
| 171 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 172 | RCBA32(0x1e9c) = 0x000200f0; |
| 173 | RCBA32(0x1e98) = 0x000c0801; |
| 174 | } |
| 175 | |
| 176 | static void early_ich7_init(void) |
| 177 | { |
| 178 | uint8_t reg8; |
| 179 | uint32_t reg32; |
| 180 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 181 | /* program secondary mlt XXX byte? */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 182 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 183 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 184 | /* reset rtc power status */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 185 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 186 | reg8 &= ~(1 << 2); |
| 187 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 188 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 189 | /* usb transient disconnect */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 190 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 191 | reg8 |= (3 << 0); |
| 192 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 193 | |
| 194 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 195 | reg32 |= (1 << 29) | (1 << 17); |
| 196 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 197 | |
| 198 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 199 | reg32 |= (1 << 31) | (1 << 27); |
| 200 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 201 | |
| 202 | RCBA32(0x0088) = 0x0011d000; |
| 203 | RCBA16(0x01fc) = 0x060f; |
| 204 | RCBA32(0x01f4) = 0x86000040; |
| 205 | RCBA32(0x0214) = 0x10030549; |
| 206 | RCBA32(0x0218) = 0x00020504; |
| 207 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 208 | reg32 = RCBA32(GCS); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 209 | reg32 |= (1 << 6); |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 210 | RCBA32(GCS) = reg32; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 211 | reg32 = RCBA32(0x3430); |
| 212 | reg32 &= ~(3 << 0); |
| 213 | reg32 |= (1 << 0); |
| 214 | RCBA32(0x3430) = reg32; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 215 | RCBA16(0x0200) = 0x2008; |
| 216 | RCBA8(0x2027) = 0x0d; |
| 217 | RCBA16(0x3e08) |= (1 << 7); |
| 218 | RCBA16(0x3e48) |= (1 << 7); |
| 219 | RCBA32(0x3e0e) |= (1 << 7); |
| 220 | RCBA32(0x3e4e) |= (1 << 7); |
| 221 | |
Elyes HAOUAS | 571fb1f | 2016-10-07 12:46:28 +0200 | [diff] [blame] | 222 | /* next step only on ich7m b0 and later: */ |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 223 | reg32 = RCBA32(0x2034); |
| 224 | reg32 &= ~(0x0f << 16); |
| 225 | reg32 |= (5 << 16); |
| 226 | RCBA32(0x2034) = reg32; |
| 227 | } |
| 228 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 229 | void mainboard_romstage_entry(unsigned long bist) |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 230 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 231 | int s3resume = 0; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 232 | const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; |
| 233 | |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 234 | if (bist == 0) |
| 235 | enable_lapic(); |
| 236 | |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 237 | ich7_enable_lpc(); |
| 238 | |
| 239 | /* Set up the console */ |
| 240 | console_init(); |
| 241 | |
| 242 | /* Halt if there was a built in self test failure */ |
| 243 | report_bist_failure(bist); |
| 244 | |
| 245 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 246 | printk(BIOS_DEBUG, |
| 247 | "Soft reset detected, rebooting properly.\n"); |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 248 | system_reset(); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | /* Perform some early chipset initialization required |
| 252 | * before RAM initialization can work |
| 253 | */ |
| 254 | i945_early_initialization(); |
| 255 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 256 | s3resume = southbridge_detect_s3_resume(); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 257 | |
| 258 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 259 | enable_smbus(); |
| 260 | |
| 261 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 262 | dump_spd_registers(); |
| 263 | #endif |
| 264 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 265 | sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 266 | |
| 267 | /* Perform some initialization that must run before stage2 */ |
| 268 | early_ich7_init(); |
| 269 | |
| 270 | /* This should probably go away. Until now it is required |
| 271 | * and mainboard specific |
| 272 | */ |
| 273 | rcba_config(); |
| 274 | |
| 275 | /* Chipset Errata! */ |
| 276 | fixup_i945_errata(); |
| 277 | |
| 278 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 279 | i945_late_initialization(s3resume); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 280 | } |