Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 24 | |
| 25 | #include <stdint.h> |
| 26 | #include <string.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
Edward O'Callaghan | cea4557 | 2014-11-19 12:08:24 +1100 | [diff] [blame^] | 30 | #include <cpu/intel/romstage.h> |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 31 | #include <cpu/x86/lapic.h> |
| 32 | #include <lib.h> |
| 33 | #include <cbmem.h> |
| 34 | #include <timestamp.h> |
| 35 | #include <pc80/mc146818rtc.h> |
| 36 | #include <console/console.h> |
| 37 | #include <cpu/x86/bist.h> |
| 38 | #include "northbridge/intel/i945/i945.h" |
| 39 | #include "northbridge/intel/i945/raminit.h" |
| 40 | #include "southbridge/intel/i82801gx/i82801gx.h" |
| 41 | |
| 42 | void setup_ich7_gpios(void) |
| 43 | { |
| 44 | printk(BIOS_DEBUG, " GPIOS..."); |
| 45 | |
| 46 | /* X60 GPIO: |
| 47 | * 1: HDD_PRESENCE# |
| 48 | * 6: Unknown (Pulled high by R215 to VCC3B) |
| 49 | * 7: BDC_PRESENCE# |
| 50 | * 8: H8_WAKE# |
| 51 | * 9: RTC_BAT_IN# |
| 52 | * 10: Unknown (Pulled high by R700 to VCC3M) |
| 53 | * 12: H8SCI# |
| 54 | * 13: SLICE_ON_3M# |
| 55 | * 14: Unknown (Pulled high by R321 to VCC3) |
| 56 | * 15: Unknown (Pulled high by R258 to VCC3) |
| 57 | * 19: Unknown (Pulled low by R594) |
| 58 | * 21: Unknown (Pulled high by R145 to VCC3) |
| 59 | * 22: FWH_WP# |
| 60 | * 25: MDC_KILL# |
| 61 | * 33: HDD_PRESENCE_2# |
| 62 | * 35: CLKREQ_SATA# |
| 63 | * 36: PLANARID0 |
| 64 | * 37: PLANARID1 |
| 65 | * 38: PLANARID2 |
| 66 | * 39: PLANARID3 |
| 67 | * 48: FWH_TBL# |
| 68 | */ |
| 69 | |
| 70 | outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 71 | outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 72 | outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 73 | /* Output Control Registers */ |
| 74 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 75 | /* Input Control Registers */ |
| 76 | outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 77 | outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 78 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 79 | outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 80 | } |
| 81 | |
| 82 | static void ich7_enable_lpc(void) |
| 83 | { |
| 84 | // Enable Serial IRQ |
| 85 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 86 | |
| 87 | // I/O Decode Ranges |
| 88 | // X60: 0x0210 == 00000010 00010000 |
| 89 | // Macbook21: 0x0010 == 00000000 00010000 |
| 90 | // Bit 9:8 LPT Decode Range. This field determines which range to |
| 91 | // decode for the LPT Port. |
| 92 | // 00 = 378h 37Fh and 778h 77Fh |
| 93 | // 10 = 3BCh 3BEh and 7BCh 7BEh |
| 94 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 95 | |
| 96 | // LPC_EN--LPC I/F Enables Register |
| 97 | // X60: 0x1f0d == 00011111 00001101 |
| 98 | // Macbook21: 0x3807 == 00111000 00000111 |
| 99 | // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. |
| 100 | // 0 = Disable. |
| 101 | // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh |
| 102 | // to the LPC interface. This range is used for a |
| 103 | // microcontroller. |
| 104 | // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. |
| 105 | // 0 = Disable. |
| 106 | // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh |
| 107 | // to the LPC interface. This range is used for |
| 108 | // Super I/O devices. |
| 109 | // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. |
| 110 | // 0 = Disable. |
| 111 | // 1 = Enables the decoding of the I/O locations 62h and 66h |
| 112 | // to the LPC interface. This range is used for a |
| 113 | // microcontroller. |
| 114 | // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. |
| 115 | // 0 = Disable. |
| 116 | // 1 = Enables the decoding of the I/O locations 60h and 64h |
| 117 | // to the LPC interface. This range is used for a |
| 118 | // microcontroller. |
| 119 | // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable |
| 120 | // 0 = Disable. |
| 121 | // 1 = Enables the decoding of the I/O locations 208h to 20Fh |
| 122 | // to the LPC interface. This range is used for a gameport. |
| 123 | // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable |
| 124 | // 0 = Disable. |
| 125 | // 1 = Enables the decoding of the I/O locations 200h to 207h |
| 126 | // to the LPC interface. This range is used for a gameport. |
| 127 | // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable |
| 128 | // 0 = Disable. |
| 129 | // 1 = Enables the decoding of the FDD range to the LPC |
| 130 | // interface. This range is selected in the LPC_FDD/LPT |
| 131 | // Decode Range Register (D31:F0:80h, bit 12). |
| 132 | // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable |
| 133 | // 0 = Disable. |
| 134 | // 1 = Enables the decoding of the LPT range to the LPC |
| 135 | // interface. This range is selected in the LPC_FDD/LPT |
| 136 | // Decode Range Register (D31:F0:80h, bit 9:8). |
| 137 | // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable |
| 138 | // 0 = Disable. |
| 139 | // 1 = Enables the decoding of the COMB range to the LPC |
| 140 | // interface. This range is selected in the LPC_COM Decode |
| 141 | // Range Register (D31:F0:80h, bits 6:4). |
| 142 | // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable |
| 143 | // 0 = Disable. |
| 144 | // 1 = Enables the decoding of the COMA range to the LPC |
| 145 | // interface. This range is selected in the LPC_COM Decode |
| 146 | // Range Register (D31:F0:80h, bits 3:2). |
| 147 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); |
| 148 | |
| 149 | /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ |
| 150 | // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 |
| 151 | // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 |
| 152 | // Bit 31:24 Reserved. |
| 153 | // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any |
| 154 | // bit position indicates that any value in the corresponding |
| 155 | // address bit in a received cycle will be treated as a |
| 156 | // match. The corresponding bit in the Address field, below, |
| 157 | // is ignored. The mask is only provided for the lower 6 bits |
| 158 | // of the DWord address, allowing for decoding blocks up to |
| 159 | // 256 bytes in size. |
| 160 | // Bit 17:16 Reserved. |
| 161 | // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This |
| 162 | // address is aligned on a 128-byte boundary, and must have |
| 163 | // address lines 31:16 as 0. NOTE: The Intel ICH7 does not |
| 164 | // provide decode down to the word or byte level. |
| 165 | // Bit 1 Reserved. |
| 166 | // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. |
| 167 | // 0 = Disable. |
| 168 | // 1 = Enable the GEN1 I/O range to be forwarded to the LPC |
| 169 | // I/F |
| 170 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); |
| 171 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); |
| 172 | |
| 173 | /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ |
| 174 | // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 |
| 175 | // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 |
| 176 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); |
| 177 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); |
| 178 | |
| 179 | /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ |
| 180 | // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 |
| 181 | // Macbook21: 0x0000 0x0000 |
| 182 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? |
| 183 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); |
| 184 | |
| 185 | /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ |
| 186 | // X60: 0x0000 0x0000 |
| 187 | // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 |
| 188 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); |
| 189 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); |
| 190 | } |
| 191 | |
| 192 | static void rcba_config(void) |
| 193 | { |
| 194 | /* V0CTL Virtual Channel 0 Resource Control */ |
| 195 | RCBA32(0x0014) = 0x80000001; |
| 196 | /* V1CAP Virtual Channel 1 Resource Capability */ |
| 197 | RCBA32(0x001c) = 0x03128010; |
| 198 | |
| 199 | /* Device 1f interrupt pin register */ |
| 200 | RCBA32(0x3100) = 0x00042210; |
| 201 | RCBA32(0x3108) = 0x10004321; |
| 202 | |
| 203 | /* PCIe Interrupts */ |
| 204 | RCBA32(0x310c) = 0x00214321; |
| 205 | /* HD Audio Interrupt */ |
| 206 | RCBA32(0x3110) = 0x00000001; |
| 207 | |
| 208 | /* dev irq route register */ |
| 209 | RCBA16(0x3140) = 0x0232; |
| 210 | RCBA16(0x3142) = 0x3246; |
| 211 | RCBA16(0x3144) = 0x0235; |
| 212 | RCBA16(0x3146) = 0x3201; |
| 213 | RCBA16(0x3148) = 0x3216; |
| 214 | |
| 215 | /* Enable IOAPIC */ |
| 216 | RCBA8(0x31ff) = 0x03; |
| 217 | |
| 218 | /* Enable upper 128bytes of CMOS */ |
| 219 | RCBA32(0x3400) = (1 << 2); |
| 220 | |
| 221 | /* Disable unused devices */ |
| 222 | RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; |
| 223 | RCBA32(0x3418) |= (1 << 0); // Required. |
| 224 | |
| 225 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 226 | // RCBA32(0x1e84) = 0x00020001; |
| 227 | // RCBA32(0x1e80) = 0x0000fe01; |
| 228 | |
| 229 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 230 | RCBA32(0x1e9c) = 0x000200f0; |
| 231 | RCBA32(0x1e98) = 0x000c0801; |
| 232 | } |
| 233 | |
| 234 | static void early_ich7_init(void) |
| 235 | { |
| 236 | uint8_t reg8; |
| 237 | uint32_t reg32; |
| 238 | |
| 239 | // program secondary mlt XXX byte? |
| 240 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 241 | |
| 242 | // reset rtc power status |
| 243 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 244 | reg8 &= ~(1 << 2); |
| 245 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 246 | |
| 247 | // usb transient disconnect |
| 248 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 249 | reg8 |= (3 << 0); |
| 250 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 251 | |
| 252 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 253 | reg32 |= (1 << 29) | (1 << 17); |
| 254 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 255 | |
| 256 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 257 | reg32 |= (1 << 31) | (1 << 27); |
| 258 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 259 | |
| 260 | RCBA32(0x0088) = 0x0011d000; |
| 261 | RCBA16(0x01fc) = 0x060f; |
| 262 | RCBA32(0x01f4) = 0x86000040; |
| 263 | RCBA32(0x0214) = 0x10030549; |
| 264 | RCBA32(0x0218) = 0x00020504; |
| 265 | RCBA8(0x0220) = 0xc5; |
| 266 | reg32 = RCBA32(0x3410); |
| 267 | reg32 |= (1 << 6); |
| 268 | RCBA32(0x3410) = reg32; |
| 269 | reg32 = RCBA32(0x3430); |
| 270 | reg32 &= ~(3 << 0); |
| 271 | reg32 |= (1 << 0); |
| 272 | RCBA32(0x3430) = reg32; |
| 273 | RCBA32(0x3418) |= (1 << 0); |
| 274 | RCBA16(0x0200) = 0x2008; |
| 275 | RCBA8(0x2027) = 0x0d; |
| 276 | RCBA16(0x3e08) |= (1 << 7); |
| 277 | RCBA16(0x3e48) |= (1 << 7); |
| 278 | RCBA32(0x3e0e) |= (1 << 7); |
| 279 | RCBA32(0x3e4e) |= (1 << 7); |
| 280 | |
| 281 | // next step only on ich7m b0 and later: |
| 282 | reg32 = RCBA32(0x2034); |
| 283 | reg32 &= ~(0x0f << 16); |
| 284 | reg32 |= (5 << 16); |
| 285 | RCBA32(0x2034) = reg32; |
| 286 | } |
| 287 | |
| 288 | void main(unsigned long bist) |
| 289 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 290 | int s3resume = 0; |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 291 | const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; |
| 292 | |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 293 | timestamp_init(get_initial_timestamp()); |
| 294 | timestamp_add_now(TS_START_ROMSTAGE); |
| 295 | |
| 296 | if (bist == 0) |
| 297 | enable_lapic(); |
| 298 | |
| 299 | /* Force PCIRST# */ |
| 300 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
| 301 | udelay(200 * 1000); |
| 302 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
| 303 | |
| 304 | ich7_enable_lpc(); |
| 305 | |
| 306 | /* Set up the console */ |
| 307 | console_init(); |
| 308 | |
| 309 | /* Halt if there was a built in self test failure */ |
| 310 | report_bist_failure(bist); |
| 311 | |
| 312 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 313 | printk(BIOS_DEBUG, |
| 314 | "Soft reset detected, rebooting properly.\n"); |
| 315 | outb(0x6, 0xcf9); |
| 316 | while (1) |
| 317 | asm("hlt"); |
| 318 | } |
| 319 | |
| 320 | /* Perform some early chipset initialization required |
| 321 | * before RAM initialization can work |
| 322 | */ |
| 323 | i945_early_initialization(); |
| 324 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 325 | s3resume = southbridge_detect_s3_resume(); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 326 | |
| 327 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 328 | enable_smbus(); |
| 329 | |
| 330 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 331 | dump_spd_registers(); |
| 332 | #endif |
| 333 | |
| 334 | timestamp_add_now(TS_BEFORE_INITRAM); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 335 | sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 336 | timestamp_add_now(TS_AFTER_INITRAM); |
| 337 | |
| 338 | /* Perform some initialization that must run before stage2 */ |
| 339 | early_ich7_init(); |
| 340 | |
| 341 | /* This should probably go away. Until now it is required |
| 342 | * and mainboard specific |
| 343 | */ |
| 344 | rcba_config(); |
| 345 | |
| 346 | /* Chipset Errata! */ |
| 347 | fixup_i945_errata(); |
| 348 | |
| 349 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 350 | i945_late_initialization(s3resume); |
Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame] | 351 | |
| 352 | timestamp_add_now(TS_END_ROMSTAGE); |
| 353 | |
| 354 | } |