Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 7 | #include <option.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 8 | #include <pc80/mc146818rtc.h> |
| 9 | #include <pc80/isa-dma.h> |
| 10 | #include <pc80/i8259.h> |
| 11 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 12 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 14 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 15 | #include <acpi/acpi.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 16 | #include <elog.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 17 | #include <acpi/acpigen.h> |
Vladimir Serbinenko | 67bfbfd | 2014-10-25 15:49:23 +0200 | [diff] [blame] | 18 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 19 | #include "chip.h" |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 20 | #include "pch.h" |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 21 | #include <southbridge/intel/common/pciehp.h> |
Kyösti Mälkki | 9099395 | 2018-05-01 19:36:25 +0300 | [diff] [blame] | 22 | #include <southbridge/intel/common/acpi_pirq_gen.h> |
Arthur Heymans | aadd1d0 | 2019-05-28 13:39:20 +0200 | [diff] [blame] | 23 | #include <southbridge/intel/common/spi.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 24 | |
| 25 | #define NMI_OFF 0 |
| 26 | |
Vladimir Serbinenko | 4695705 | 2013-11-26 01:16:20 +0100 | [diff] [blame] | 27 | typedef struct southbridge_intel_ibexpeak_config config_t; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 28 | |
| 29 | /** |
| 30 | * Set miscellanous static southbridge features. |
| 31 | * |
| 32 | * @param dev PCI device with I/O APIC control registers |
| 33 | */ |
| 34 | static void pch_enable_ioapic(struct device *dev) |
| 35 | { |
| 36 | u32 reg32; |
| 37 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 38 | set_ioapic_id(VIO_APIC_VADDR, 0x01); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 39 | /* affirm full set of redirection table entries ("write once") */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 40 | reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); |
| 41 | io_apic_write(VIO_APIC_VADDR, 0x01, reg32); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 42 | |
| 43 | /* |
| 44 | * Select Boot Configuration register (0x03) and |
| 45 | * use Processor System Bus (0x01) to deliver interrupts. |
| 46 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static void pch_enable_serial_irqs(struct device *dev) |
| 51 | { |
| 52 | /* Set packet length and toggle silent mode bit for one frame. */ |
| 53 | pci_write_config8(dev, SERIRQ_CNTL, |
| 54 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 55 | #if !CONFIG(SERIRQ_CONTINUOUS_MODE) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 56 | pci_write_config8(dev, SERIRQ_CNTL, |
| 57 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
| 58 | #endif |
| 59 | } |
| 60 | |
| 61 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 62 | * 0x00 - 0000 = Reserved |
| 63 | * 0x01 - 0001 = Reserved |
| 64 | * 0x02 - 0010 = Reserved |
| 65 | * 0x03 - 0011 = IRQ3 |
| 66 | * 0x04 - 0100 = IRQ4 |
| 67 | * 0x05 - 0101 = IRQ5 |
| 68 | * 0x06 - 0110 = IRQ6 |
| 69 | * 0x07 - 0111 = IRQ7 |
| 70 | * 0x08 - 1000 = Reserved |
| 71 | * 0x09 - 1001 = IRQ9 |
| 72 | * 0x0A - 1010 = IRQ10 |
| 73 | * 0x0B - 1011 = IRQ11 |
| 74 | * 0x0C - 1100 = IRQ12 |
| 75 | * 0x0D - 1101 = Reserved |
| 76 | * 0x0E - 1110 = IRQ14 |
| 77 | * 0x0F - 1111 = IRQ15 |
| 78 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 79 | * 0x80 - The PIRQ is not routed. |
| 80 | */ |
| 81 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 82 | static void pch_pirq_init(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 83 | { |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 84 | struct device *irq_dev; |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 85 | /* |
| 86 | * Interrupt 11 is not used by legacy devices and so can always be used for |
| 87 | * PCI interrupts. Full legacy IRQ routing is complicated and hard to |
| 88 | * get right. Fortunately all modern OS use MSI and so it's not that big of |
| 89 | * an issue anyway. Still we have to provide a reasonable default. Using |
| 90 | * interrupt 11 for it everywhere is a working default. ACPI-aware OS can |
| 91 | * move it to any interrupt and others will just leave them at default. |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 92 | */ |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 93 | const u8 pirq_routing = 11; |
| 94 | |
| 95 | pci_write_config8(dev, PIRQA_ROUT, pirq_routing); |
| 96 | pci_write_config8(dev, PIRQB_ROUT, pirq_routing); |
| 97 | pci_write_config8(dev, PIRQC_ROUT, pirq_routing); |
| 98 | pci_write_config8(dev, PIRQD_ROUT, pirq_routing); |
| 99 | |
| 100 | pci_write_config8(dev, PIRQE_ROUT, pirq_routing); |
| 101 | pci_write_config8(dev, PIRQF_ROUT, pirq_routing); |
| 102 | pci_write_config8(dev, PIRQG_ROUT, pirq_routing); |
| 103 | pci_write_config8(dev, PIRQH_ROUT, pirq_routing); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 104 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 105 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 106 | u8 int_pin=0; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 107 | |
| 108 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 109 | continue; |
| 110 | |
| 111 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 112 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 113 | if (int_pin == 0) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 114 | continue; |
| 115 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 116 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 120 | static void pch_gpi_routing(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 121 | { |
| 122 | /* Get the chip configuration */ |
| 123 | config_t *config = dev->chip_info; |
| 124 | u32 reg32 = 0; |
| 125 | |
| 126 | /* An array would be much nicer here, or some |
| 127 | * other method of doing this. |
| 128 | */ |
| 129 | reg32 |= (config->gpi0_routing & 0x03) << 0; |
| 130 | reg32 |= (config->gpi1_routing & 0x03) << 2; |
| 131 | reg32 |= (config->gpi2_routing & 0x03) << 4; |
| 132 | reg32 |= (config->gpi3_routing & 0x03) << 6; |
| 133 | reg32 |= (config->gpi4_routing & 0x03) << 8; |
| 134 | reg32 |= (config->gpi5_routing & 0x03) << 10; |
| 135 | reg32 |= (config->gpi6_routing & 0x03) << 12; |
| 136 | reg32 |= (config->gpi7_routing & 0x03) << 14; |
| 137 | reg32 |= (config->gpi8_routing & 0x03) << 16; |
| 138 | reg32 |= (config->gpi9_routing & 0x03) << 18; |
| 139 | reg32 |= (config->gpi10_routing & 0x03) << 20; |
| 140 | reg32 |= (config->gpi11_routing & 0x03) << 22; |
| 141 | reg32 |= (config->gpi12_routing & 0x03) << 24; |
| 142 | reg32 |= (config->gpi13_routing & 0x03) << 26; |
| 143 | reg32 |= (config->gpi14_routing & 0x03) << 28; |
| 144 | reg32 |= (config->gpi15_routing & 0x03) << 30; |
| 145 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 146 | pci_write_config32(dev, GPIO_ROUT, reg32); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 147 | } |
| 148 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 149 | static void pch_power_options(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 150 | { |
| 151 | u8 reg8; |
| 152 | u16 reg16, pmbase; |
| 153 | u32 reg32; |
| 154 | const char *state; |
| 155 | /* Get the chip configuration */ |
| 156 | config_t *config = dev->chip_info; |
| 157 | |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 158 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 159 | int nmi_option; |
| 160 | |
| 161 | /* Which state do we want to goto after g3 (power restored)? |
| 162 | * 0 == S0 Full On |
| 163 | * 1 == S5 Soft Off |
| 164 | * |
| 165 | * If the option is not existent (Laptops), use Kconfig setting. |
| 166 | */ |
| 167 | get_option(&pwr_on, "power_on_after_fail"); |
| 168 | |
| 169 | reg16 = pci_read_config16(dev, GEN_PMCON_3); |
| 170 | reg16 &= 0xfffe; |
| 171 | switch (pwr_on) { |
| 172 | case MAINBOARD_POWER_OFF: |
| 173 | reg16 |= 1; |
| 174 | state = "off"; |
| 175 | break; |
| 176 | case MAINBOARD_POWER_ON: |
| 177 | reg16 &= ~1; |
| 178 | state = "on"; |
| 179 | break; |
| 180 | case MAINBOARD_POWER_KEEP: |
| 181 | reg16 &= ~1; |
| 182 | state = "state keep"; |
| 183 | break; |
| 184 | default: |
| 185 | state = "undefined"; |
| 186 | } |
| 187 | |
| 188 | reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ |
| 189 | reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ |
| 190 | |
| 191 | reg16 &= ~(1 << 10); |
| 192 | reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ |
| 193 | |
| 194 | reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ |
| 195 | |
| 196 | pci_write_config16(dev, GEN_PMCON_3, reg16); |
| 197 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 198 | |
| 199 | /* Set up NMI on errors. */ |
| 200 | reg8 = inb(0x61); |
| 201 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 202 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 203 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 204 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 205 | outb(reg8, 0x61); |
| 206 | |
| 207 | reg8 = inb(0x70); |
| 208 | nmi_option = NMI_OFF; |
| 209 | get_option(&nmi_option, "nmi"); |
| 210 | if (nmi_option) { |
| 211 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
| 212 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 213 | } else { |
| 214 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 215 | reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 216 | } |
| 217 | outb(reg8, 0x70); |
| 218 | |
| 219 | /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ |
| 220 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 221 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 222 | reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME |
Kyösti Mälkki | 9446447 | 2020-06-13 13:45:42 +0300 | [diff] [blame] | 223 | if (CONFIG(DEBUG_PERIODIC_SMI)) |
| 224 | reg16 |= (3 << 0); // Periodic SMI every 8s |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 225 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 226 | |
| 227 | // Set the board's GPI routing. |
| 228 | pch_gpi_routing(dev); |
| 229 | |
| 230 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 231 | |
| 232 | outl(config->gpe0_en, pmbase + GPE0_EN); |
| 233 | outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); |
| 234 | |
| 235 | /* Set up power management block and determine sleep mode */ |
| 236 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 237 | reg32 &= ~(7 << 10); // SLP_TYP |
| 238 | reg32 |= (1 << 0); // SCI_EN |
| 239 | outl(reg32, pmbase + 0x04); |
| 240 | |
| 241 | /* Clear magic status bits to prevent unexpected wake */ |
Angel Pons | 42b4e4e | 2019-09-18 10:58:53 +0200 | [diff] [blame] | 242 | reg32 = RCBA32(PRSTS); |
| 243 | reg32 |= (1 << 5) | (1 << 4) | (1 << 0); |
| 244 | RCBA32(PRSTS) = reg32; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 245 | |
Angel Pons | 42b4e4e | 2019-09-18 10:58:53 +0200 | [diff] [blame] | 246 | /* FIXME: Does this even exist? */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 247 | reg32 = RCBA32(0x3f02); |
| 248 | reg32 &= ~0xf; |
| 249 | RCBA32(0x3f02) = reg32; |
| 250 | } |
| 251 | |
| 252 | static void pch_rtc_init(struct device *dev) |
| 253 | { |
| 254 | u8 reg8; |
| 255 | int rtc_failed; |
| 256 | |
| 257 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 258 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 259 | if (rtc_failed) { |
| 260 | reg8 &= ~RTC_BATTERY_DEAD; |
| 261 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 262 | elog_add_event(ELOG_TYPE_RTC_RESET); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 263 | } |
| 264 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 265 | |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 266 | cmos_init(rtc_failed); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | static void mobile5_pm_init(struct device *dev) |
| 270 | { |
| 271 | int i; |
| 272 | |
| 273 | printk(BIOS_DEBUG, "Mobile 5 PM init\n"); |
| 274 | pci_write_config8(dev, 0xa9, 0x47); |
| 275 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 276 | RCBA32(0x1d44) = 0x00000000; |
| 277 | (void)RCBA32(0x1d44); |
| 278 | RCBA32(0x1d48) = 0x00030000; |
| 279 | (void)RCBA32(0x1d48); |
| 280 | RCBA32(0x1e80) = 0x000c0801; |
| 281 | (void)RCBA32(0x1e80); |
| 282 | RCBA32(0x1e84) = 0x000200f0; |
| 283 | (void)RCBA32(0x1e84); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 284 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 285 | const u32 rcba2010[] = { |
| 286 | /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, |
| 287 | /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 |
| 288 | }; |
| 289 | for (i = 0; i < ARRAY_SIZE(rcba2010); i++) { |
| 290 | RCBA32(0x2010 + 4 * i) = rcba2010[i]; |
| 291 | RCBA32(0x2010 + 4 * i); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 292 | } |
| 293 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 294 | RCBA32(0x2100) = 0x00000000; |
| 295 | (void)RCBA32(0x2100); |
| 296 | RCBA32(0x2104) = 0x00000757; |
| 297 | (void)RCBA32(0x2104); |
| 298 | RCBA32(0x2108) = 0x00170001; |
| 299 | (void)RCBA32(0x2108); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 300 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 301 | RCBA32(0x211c) = 0x00000000; |
| 302 | (void)RCBA32(0x211c); |
| 303 | RCBA32(0x2120) = 0x00010000; |
| 304 | (void)RCBA32(0x2120); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 305 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 306 | RCBA32(0x21fc) = 0x00000000; |
| 307 | (void)RCBA32(0x21fc); |
| 308 | RCBA32(0x2200) = 0x20000044; |
| 309 | (void)RCBA32(0x2200); |
| 310 | RCBA32(0x2204) = 0x00000001; |
| 311 | (void)RCBA32(0x2204); |
| 312 | RCBA32(0x2208) = 0x00003457; |
| 313 | (void)RCBA32(0x2208); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 314 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 315 | const u32 rcba2210[] = { |
| 316 | /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, |
| 317 | /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, |
| 318 | /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, |
| 319 | /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, |
| 320 | /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, |
| 321 | /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, |
| 322 | /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 |
| 323 | }; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 324 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 325 | for (i = 0; i < ARRAY_SIZE(rcba2210); i++) { |
| 326 | RCBA32(0x2210 + 4 * i) = rcba2210[i]; |
| 327 | RCBA32(0x2210 + 4 * i); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 328 | } |
| 329 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 330 | const u32 rcba2300[] = { |
| 331 | /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, |
| 332 | /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, |
| 333 | /* 2320: */ 0xcccc0cfc, 0x0fbb0fff |
| 334 | }; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 335 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 336 | for (i = 0; i < ARRAY_SIZE(rcba2300); i++) { |
| 337 | RCBA32(0x2300 + 4 * i) = rcba2300[i]; |
| 338 | RCBA32(0x2300 + 4 * i); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 339 | } |
| 340 | |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 341 | RCBA32(0x37fc) = 0x00000000; |
| 342 | (void)RCBA32(0x37fc); |
| 343 | RCBA32(0x3dfc) = 0x00000000; |
| 344 | (void)RCBA32(0x3dfc); |
| 345 | RCBA32(0x3e7c) = 0xffffffff; |
| 346 | (void)RCBA32(0x3e7c); |
| 347 | RCBA32(0x3efc) = 0x00000000; |
| 348 | (void)RCBA32(0x3efc); |
| 349 | RCBA32(0x3f00) = 0x0000010b; |
| 350 | (void)RCBA32(0x3f00); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | static void enable_hpet(void) |
| 354 | { |
| 355 | u32 reg32; |
| 356 | |
| 357 | /* Move HPET to default address 0xfed00000 and enable it */ |
| 358 | reg32 = RCBA32(HPTC); |
| 359 | reg32 |= (1 << 7); // HPET Address Enable |
| 360 | reg32 &= ~(3 << 0); |
| 361 | RCBA32(HPTC) = reg32; |
Arthur Heymans | 37e1d93 | 2019-10-02 14:33:34 +0200 | [diff] [blame] | 362 | RCBA32(HPTC); /* Read back for it to work */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 363 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 364 | write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 365 | } |
| 366 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 367 | static void enable_clock_gating(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 368 | { |
| 369 | u32 reg32; |
| 370 | u16 reg16; |
| 371 | |
| 372 | RCBA32_AND_OR(0x2234, ~0UL, 0xf); |
| 373 | |
| 374 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 375 | reg16 |= (1 << 2) | (1 << 11); |
| 376 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 377 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 378 | reg32 = RCBA32(CG); |
| 379 | reg32 |= (1 << 31); |
| 380 | reg32 |= (1 << 29) | (1 << 28); |
| 381 | reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); |
| 382 | reg32 |= (1 << 16); |
| 383 | reg32 |= (1 << 17); |
| 384 | reg32 |= (1 << 18); |
| 385 | reg32 |= (1 << 22); |
| 386 | reg32 |= (1 << 23); |
| 387 | reg32 &= ~(1 << 20); |
| 388 | reg32 |= (1 << 19); |
| 389 | reg32 |= (1 << 0); |
| 390 | reg32 |= (0xf << 1); |
| 391 | RCBA32(CG) = reg32; |
| 392 | |
| 393 | RCBA32_OR(0x38c0, 0x7); |
| 394 | RCBA32_OR(0x36d4, 0x6680c004); |
| 395 | RCBA32_OR(0x3564, 0x3); |
| 396 | } |
| 397 | |
Vladimir Serbinenko | 456f495 | 2015-05-28 20:42:32 +0200 | [diff] [blame] | 398 | static void pch_set_acpi_mode(void) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 399 | { |
Kyösti Mälkki | ad882c3 | 2020-06-02 05:05:30 +0300 | [diff] [blame] | 400 | if (!acpi_is_wakeup_s3()) { |
| 401 | apm_control(APM_CNT_ACPI_DISABLE); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 402 | } |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 403 | } |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 404 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 405 | static void pch_fixups(struct device *dev) |
| 406 | { |
| 407 | /* |
| 408 | * Enable DMI ASPM in the PCH |
| 409 | */ |
| 410 | RCBA32_AND_OR(0x2304, ~(1 << 10), 0); |
| 411 | RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); |
| 412 | RCBA32_OR(0x21a8, 0x3); |
| 413 | } |
| 414 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 415 | static void lpc_init(struct device *dev) |
| 416 | { |
Elyes HAOUAS | bfc255a | 2020-03-07 13:05:14 +0100 | [diff] [blame] | 417 | printk(BIOS_DEBUG, "pch: %s\n", __func__); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 418 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 419 | /* IO APIC initialization. */ |
| 420 | pch_enable_ioapic(dev); |
| 421 | |
| 422 | pch_enable_serial_irqs(dev); |
| 423 | |
| 424 | /* Setup the PIRQ. */ |
| 425 | pch_pirq_init(dev); |
| 426 | |
| 427 | /* Setup power options. */ |
| 428 | pch_power_options(dev); |
| 429 | |
| 430 | /* Initialize power management */ |
Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 431 | mobile5_pm_init(dev); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 432 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 433 | /* Initialize the real time clock. */ |
| 434 | pch_rtc_init(dev); |
| 435 | |
| 436 | /* Initialize ISA DMA. */ |
| 437 | isa_dma_init(); |
| 438 | |
| 439 | /* Initialize the High Precision Event Timers, if present. */ |
| 440 | enable_hpet(); |
| 441 | |
| 442 | /* Initialize Clock Gating */ |
| 443 | enable_clock_gating(dev); |
| 444 | |
| 445 | setup_i8259(); |
| 446 | |
| 447 | /* The OS should do this? */ |
| 448 | /* Interrupt 9 should be level triggered (SCI) */ |
| 449 | i8259_configure_irq_trigger(9, 1); |
| 450 | |
Vladimir Serbinenko | 456f495 | 2015-05-28 20:42:32 +0200 | [diff] [blame] | 451 | pch_set_acpi_mode(); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 452 | |
| 453 | pch_fixups(dev); |
| 454 | } |
| 455 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 456 | static void pch_lpc_read_resources(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 457 | { |
| 458 | struct resource *res; |
| 459 | config_t *config = dev->chip_info; |
| 460 | u8 io_index = 0; |
| 461 | |
| 462 | /* Get the normal PCI resources of this device. */ |
| 463 | pci_dev_read_resources(dev); |
| 464 | |
| 465 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 466 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 467 | res->base = 0; |
| 468 | res->size = 0x1000; |
| 469 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 470 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 471 | |
| 472 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 473 | res->base = 0xff800000; |
| 474 | res->size = 0x00800000; /* 8 MB for flash */ |
| 475 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 476 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 477 | |
| 478 | res = new_resource(dev, 3); /* IOAPIC */ |
| 479 | res->base = IO_APIC_ADDR; |
| 480 | res->size = 0x00001000; |
| 481 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 482 | |
| 483 | /* Set PCH IO decode ranges if required.*/ |
| 484 | if ((config->gen1_dec & 0xFFFC) > 0x1000) { |
| 485 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 486 | res->base = config->gen1_dec & 0xFFFC; |
| 487 | res->size = (config->gen1_dec >> 16) & 0xFC; |
| 488 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 489 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 490 | } |
| 491 | |
| 492 | if ((config->gen2_dec & 0xFFFC) > 0x1000) { |
| 493 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 494 | res->base = config->gen2_dec & 0xFFFC; |
| 495 | res->size = (config->gen2_dec >> 16) & 0xFC; |
| 496 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 497 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 498 | } |
| 499 | |
| 500 | if ((config->gen3_dec & 0xFFFC) > 0x1000) { |
| 501 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 502 | res->base = config->gen3_dec & 0xFFFC; |
| 503 | res->size = (config->gen3_dec >> 16) & 0xFC; |
| 504 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 505 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 506 | } |
| 507 | |
| 508 | if ((config->gen4_dec & 0xFFFC) > 0x1000) { |
| 509 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 510 | res->base = config->gen4_dec & 0xFFFC; |
| 511 | res->size = (config->gen4_dec >> 16) & 0xFC; |
| 512 | res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | |
| 513 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 514 | } |
| 515 | } |
| 516 | |
Elyes HAOUAS | be84140 | 2018-05-13 13:40:39 +0200 | [diff] [blame] | 517 | static void pch_lpc_enable(struct device *dev) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 518 | { |
| 519 | /* Enable PCH Display Port */ |
| 520 | RCBA16(DISPBDF) = 0x0010; |
| 521 | RCBA32_OR(FD2, PCH_ENABLE_DBDF); |
| 522 | |
| 523 | pch_enable(dev); |
| 524 | } |
| 525 | |
Kyösti Mälkki | 9099395 | 2018-05-01 19:36:25 +0300 | [diff] [blame] | 526 | static const char *lpc_acpi_name(const struct device *dev) |
| 527 | { |
| 528 | return "LPCB"; |
| 529 | } |
| 530 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 531 | static void southbridge_fill_ssdt(const struct device *device) |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 532 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 533 | struct device *dev = pcidev_on_root(0x1f, 0); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 534 | config_t *chip = dev->chip_info; |
| 535 | |
| 536 | intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); |
Kyösti Mälkki | 9099395 | 2018-05-01 19:36:25 +0300 | [diff] [blame] | 537 | intel_acpi_gen_def_acpi_pirq(dev); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 538 | } |
| 539 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 540 | static void lpc_final(struct device *dev) |
| 541 | { |
Arthur Heymans | aadd1d0 | 2019-05-28 13:39:20 +0200 | [diff] [blame] | 542 | spi_finalize_ops(); |
| 543 | |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 544 | /* Call SMM finalize() handlers before resume */ |
Kyösti Mälkki | ad882c3 | 2020-06-02 05:05:30 +0300 | [diff] [blame] | 545 | if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || |
| 546 | acpi_is_wakeup_s3()) { |
| 547 | apm_control(APM_CNT_FINALIZE); |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 548 | } |
| 549 | } |
| 550 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 551 | static struct device_operations device_ops = { |
| 552 | .read_resources = pch_lpc_read_resources, |
| 553 | .set_resources = pci_dev_set_resources, |
Arthur Heymans | 3b452e0 | 2019-10-03 09:16:10 +0200 | [diff] [blame] | 554 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 555 | .acpi_fill_ssdt = southbridge_fill_ssdt, |
Kyösti Mälkki | 9099395 | 2018-05-01 19:36:25 +0300 | [diff] [blame] | 556 | .acpi_name = lpc_acpi_name, |
Angel Pons | 77f340a | 2020-10-17 18:39:04 +0200 | [diff] [blame] | 557 | .write_acpi_tables = acpi_write_hpet, |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 558 | .init = lpc_init, |
Bill XIE | d533b16 | 2017-08-22 16:26:22 +0800 | [diff] [blame] | 559 | .final = lpc_final, |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 560 | .enable = pch_lpc_enable, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 561 | .scan_bus = scan_static_bus, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 562 | .ops_pci = &pci_dev_ops_pci, |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 563 | }; |
| 564 | |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 565 | static const unsigned short pci_device_ids[] = { |
Angel Pons | 4562183 | 2021-02-24 22:02:04 +0100 | [diff] [blame^] | 566 | PCI_DID_INTEL_IBEXPEAK_LPC_P55, |
| 567 | PCI_DID_INTEL_IBEXPEAK_LPC_PM55, |
| 568 | PCI_DID_INTEL_IBEXPEAK_LPC_H55, |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 569 | PCI_DID_INTEL_IBEXPEAK_LPC_QM57, |
Angel Pons | 4562183 | 2021-02-24 22:02:04 +0100 | [diff] [blame^] | 570 | PCI_DID_INTEL_IBEXPEAK_LPC_H57, |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 571 | PCI_DID_INTEL_IBEXPEAK_LPC_HM55, |
Angel Pons | 4562183 | 2021-02-24 22:02:04 +0100 | [diff] [blame^] | 572 | PCI_DID_INTEL_IBEXPEAK_LPC_Q57, |
| 573 | PCI_DID_INTEL_IBEXPEAK_LPC_HM57, |
| 574 | PCI_DID_INTEL_IBEXPEAK_LPC_QS57, |
| 575 | PCI_DID_INTEL_IBEXPEAK_LPC_3400, |
| 576 | PCI_DID_INTEL_IBEXPEAK_LPC_3420, |
| 577 | PCI_DID_INTEL_IBEXPEAK_LPC_3450, |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 578 | 0 |
| 579 | }; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 580 | |
| 581 | static const struct pci_driver pch_lpc __pci_driver = { |
| 582 | .ops = &device_ops, |
| 583 | .vendor = PCI_VENDOR_ID_INTEL, |
| 584 | .devices = pci_device_ids, |
| 585 | }; |