Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 5 | |
Jacob Garber | 4a21647 | 2019-12-27 14:18:32 -0700 | [diff] [blame] | 6 | #include "gm45.h" |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 7 | |
Arthur Heymans | be9533a | 2019-10-12 14:35:25 +0200 | [diff] [blame] | 8 | void bootblock_early_northbridge_init(void) |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 9 | { |
| 10 | uint32_t reg; |
| 11 | |
| 12 | /* |
| 13 | * The "io" variant of the config access is explicitly used to |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 14 | * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to |
Elyes HAOUAS | 4537332 | 2021-01-16 15:01:43 +0100 | [diff] [blame^] | 15 | * true. That way all subsequent non-explicit config accesses use |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 16 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 17 | * the first thing called in the non-asm boot block code. The final |
| 18 | * assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 19 | * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 20 | * |
| 21 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 22 | * 4GiB. |
| 23 | */ |
| 24 | reg = 0; |
| 25 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); |
| 26 | reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ |
| 27 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); |
| 28 | } |