Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 14 | #include <arch/io.h> |
| 15 | |
| 16 | /* Just re-define these instead of including gm45.h. It blows up romcc. */ |
| 17 | #define D0F0_PCIEXBAR_LO 0x60 |
| 18 | #define D0F0_PCIEXBAR_HI 0x64 |
| 19 | |
| 20 | static void bootblock_northbridge_init(void) |
| 21 | { |
| 22 | uint32_t reg; |
| 23 | |
| 24 | /* |
| 25 | * The "io" variant of the config access is explicitly used to |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 26 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 27 | * to true. That way all subsequent non-explicit config accesses use |
| 28 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 29 | * the first thing called in the non-asm boot block code. The final |
| 30 | * assumption is that no assembly code is using the |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 31 | * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. |
Kyösti Mälkki | 35a7249 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 32 | * |
| 33 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 34 | * 4GiB. |
| 35 | */ |
| 36 | reg = 0; |
| 37 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); |
| 38 | reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ |
| 39 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); |
| 40 | } |