Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ |
| 4 | #define _SOC_INTEL_BROADWELL_CHIP_H_ |
| 5 | |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 6 | #include <drivers/intel/gma/i915.h> |
Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | struct soc_intel_broadwell_config { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 10 | /* |
| 11 | * Digital Port Hotplug Enable: |
| 12 | * 0x04 = Enabled, 2ms short pulse |
| 13 | * 0x05 = Enabled, 4.5ms short pulse |
| 14 | * 0x06 = Enabled, 6ms short pulse |
| 15 | * 0x07 = Enabled, 100ms short pulse |
| 16 | */ |
| 17 | u8 gpu_dp_b_hotplug; |
| 18 | u8 gpu_dp_c_hotplug; |
| 19 | u8 gpu_dp_d_hotplug; |
| 20 | |
| 21 | /* Panel power sequence timings */ |
Michael Niewöhner | 44fa0d4 | 2020-12-28 15:00:39 +0100 | [diff] [blame^] | 22 | u16 gpu_panel_power_cycle_delay_ms; |
| 23 | u16 gpu_panel_power_up_delay_ms; |
| 24 | u16 gpu_panel_power_down_delay_ms; |
| 25 | u16 gpu_panel_power_backlight_on_delay_ms; |
| 26 | u16 gpu_panel_power_backlight_off_delay_ms; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 27 | |
| 28 | /* Panel backlight settings */ |
Nico Huber | 3b57a7c | 2019-10-08 20:24:05 +0200 | [diff] [blame] | 29 | unsigned int gpu_pch_backlight_pwm_hz; |
| 30 | enum { |
| 31 | GPU_BACKLIGHT_POLARITY_HIGH = 0, |
| 32 | GPU_BACKLIGHT_POLARITY_LOW, |
| 33 | } gpu_pch_backlight_polarity; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * Graphics CD Clock Frequency |
| 37 | * 0 = 337.5MHz |
| 38 | * 1 = 450MHz |
| 39 | * 2 = 540MHz |
| 40 | * 3 = 675MHz |
| 41 | */ |
| 42 | int cdclk; |
| 43 | |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 44 | struct i915_gpu_controller_info gfx; |
| 45 | |
Duncan Laurie | ff0f460 | 2015-01-20 07:53:27 -0800 | [diff] [blame] | 46 | /* |
| 47 | * Minimum voltage for C6/C7 state: |
| 48 | * 0x67 = 1.6V (full swing) |
| 49 | * ... |
| 50 | * 0x79 = 1.7V |
| 51 | * ... |
| 52 | * 0x83 = 1.8V (no swing) |
| 53 | */ |
| 54 | int vr_cpu_min_vid; |
| 55 | |
| 56 | /* |
| 57 | * Set slow VR ramp rate on C-state exit: |
| 58 | * 0 = Fast VR ramp rate / 2 |
| 59 | * 1 = Fast VR ramp rate / 4 |
| 60 | * 2 = Fast VR ramp rate / 8 |
| 61 | * 3 = Fast VR ramp rate / 16 |
| 62 | */ |
| 63 | int vr_slow_ramp_rate_set; |
| 64 | |
| 65 | /* Enable slow VR ramp rate */ |
| 66 | int vr_slow_ramp_rate_enable; |
| 67 | |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 68 | /* Enable S0iX support */ |
| 69 | int s0ix_enable; |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 70 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 71 | /* TCC activation offset */ |
Angel Pons | 643c82e | 2020-09-24 16:43:21 +0200 | [diff] [blame] | 72 | uint32_t tcc_offset; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | typedef struct soc_intel_broadwell_config config_t; |
| 76 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 77 | #endif |