Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2, or (at your option) |
| 9 | * any later verion of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 17 | #include <arch/acpi.h> |
| 18 | #include <types.h> |
| 19 | #include <string.h> |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 20 | #include <cbfs.h> |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <device/pci_ops.h> |
Patrick Rudolph | bac2303 | 2017-06-30 15:18:23 +0200 | [diff] [blame] | 25 | #include <console/console.h> |
| 26 | #include <cbmem.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 27 | #include "intel_bios.h" |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 28 | #include "opregion.h" |
| 29 | |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 30 | __weak |
| 31 | const char *mainboard_vbt_filename(void) |
| 32 | { |
| 33 | return "vbt.bin"; |
| 34 | } |
| 35 | |
| 36 | static char vbt_data[8 * KiB]; |
Aaron Durbin | 44f8065 | 2018-05-11 11:43:52 -0600 | [diff] [blame^] | 37 | static size_t vbt_data_sz; |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 38 | |
| 39 | void *locate_vbt(size_t *vbt_size) |
| 40 | { |
| 41 | uint32_t vbtsig = 0; |
| 42 | |
Aaron Durbin | 44f8065 | 2018-05-11 11:43:52 -0600 | [diff] [blame^] | 43 | if (vbt_data_sz != 0) { |
| 44 | if (vbt_size) |
| 45 | *vbt_size = vbt_data_sz; |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 46 | return (void *)vbt_data; |
Aaron Durbin | 44f8065 | 2018-05-11 11:43:52 -0600 | [diff] [blame^] | 47 | } |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 48 | |
| 49 | const char *filename = mainboard_vbt_filename(); |
| 50 | |
| 51 | size_t file_size = cbfs_boot_load_file(filename, |
| 52 | vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW); |
| 53 | |
| 54 | if (file_size == 0) |
| 55 | return NULL; |
| 56 | |
| 57 | if (vbt_size) |
| 58 | *vbt_size = file_size; |
| 59 | |
| 60 | memcpy(&vbtsig, vbt_data, sizeof(vbtsig)); |
| 61 | if (vbtsig != VBT_SIGNATURE) { |
| 62 | printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n"); |
| 63 | return NULL; |
| 64 | } |
| 65 | |
| 66 | printk(BIOS_INFO, "Found a VBT of %zu bytes after decompression\n", |
| 67 | file_size); |
Aaron Durbin | 44f8065 | 2018-05-11 11:43:52 -0600 | [diff] [blame^] | 68 | vbt_data_sz = file_size; |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 69 | |
| 70 | return (void *)vbt_data; |
| 71 | } |
| 72 | |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 73 | /* Write ASLS PCI register and prepare SWSCI register. */ |
| 74 | void intel_gma_opregion_register(uintptr_t opregion) |
| 75 | { |
Elyes HAOUAS | 263076c | 2018-05-02 21:54:59 +0200 | [diff] [blame] | 76 | struct device *igd; |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 77 | u16 reg16; |
Matt DeVillier | 681ef51 | 2018-02-11 01:17:01 -0600 | [diff] [blame] | 78 | u16 sci_reg; |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 79 | |
| 80 | igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); |
| 81 | if (!igd || !igd->enabled) |
| 82 | return; |
| 83 | |
| 84 | /* |
| 85 | * Intel BIOS Specification |
| 86 | * Chapter 5.3.7 "Initialize Hardware State" |
| 87 | */ |
| 88 | pci_write_config32(igd, ASLS, opregion); |
| 89 | |
| 90 | /* |
Matt DeVillier | 681ef51 | 2018-02-11 01:17:01 -0600 | [diff] [blame] | 91 | * Atom-based platforms use a combined SMI/SCI register, |
| 92 | * whereas non-Atom platforms use a separate SCI register. |
| 93 | */ |
| 94 | if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) |
| 95 | sci_reg = SWSMISCI; |
| 96 | else |
| 97 | sci_reg = SWSCI; |
| 98 | |
| 99 | /* |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 100 | * Intel's Windows driver relies on this: |
| 101 | * Intel BIOS Specification |
| 102 | * Chapter 5.4 "ASL Software SCI Handler" |
| 103 | */ |
Matt DeVillier | 681ef51 | 2018-02-11 01:17:01 -0600 | [diff] [blame] | 104 | reg16 = pci_read_config16(igd, sci_reg); |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 105 | reg16 &= ~GSSCIE; |
| 106 | reg16 |= SMISCISEL; |
Matt DeVillier | 681ef51 | 2018-02-11 01:17:01 -0600 | [diff] [blame] | 107 | pci_write_config16(igd, sci_reg, reg16); |
Patrick Rudolph | fa47042 | 2017-06-20 17:49:53 +0200 | [diff] [blame] | 108 | } |
Patrick Rudolph | bac2303 | 2017-06-30 15:18:23 +0200 | [diff] [blame] | 109 | |
| 110 | /* Restore ASLS register on S3 resume and prepare SWSCI. */ |
| 111 | void intel_gma_restore_opregion(void) |
| 112 | { |
| 113 | if (acpi_is_wakeup_s3()) { |
| 114 | const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 115 | uintptr_t aslb; |
| 116 | |
| 117 | if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs))) |
| 118 | intel_gma_opregion_register(aslb); |
| 119 | else |
| 120 | printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n"); |
| 121 | } |
| 122 | } |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 123 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 124 | static enum cb_err vbt_validate(struct region_device *rdev) |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 125 | { |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 126 | uint32_t sig; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 127 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 128 | if (rdev_readat(rdev, &sig, 0, sizeof(sig)) != sizeof(sig)) |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 129 | return CB_ERR; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 130 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 131 | if (sig != VBT_SIGNATURE) |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 132 | return CB_ERR; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 133 | |
| 134 | return CB_SUCCESS; |
| 135 | } |
| 136 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 137 | static enum cb_err locate_vbt_vbios(const u8 *vbios, struct region_device *rdev) |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 138 | { |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 139 | const optionrom_header_t *oprom; |
| 140 | const optionrom_pcir_t *pcir; |
| 141 | struct region_device rd; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 142 | enum cb_err ret; |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 143 | u8 opromsize; |
| 144 | size_t offset; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 145 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 146 | // FIXME: caller should supply a region_device instead of vbios pointer |
| 147 | if (rdev_chain(&rd, &addrspace_32bit.rdev, (uintptr_t)vbios, |
| 148 | sizeof(*oprom))) |
| 149 | return CB_ERR; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 150 | |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 151 | if (rdev_readat(&rd, &opromsize, offsetof(optionrom_header_t, size), |
| 152 | sizeof(opromsize)) != sizeof(opromsize) || !opromsize) |
| 153 | return CB_ERR; |
| 154 | |
| 155 | if (rdev_chain(&rd, &addrspace_32bit.rdev, (uintptr_t)vbios, |
| 156 | opromsize * 512)) |
| 157 | return CB_ERR; |
| 158 | |
| 159 | oprom = rdev_mmap(&rd, 0, sizeof(*oprom)); |
| 160 | if (!oprom) |
| 161 | return CB_ERR; |
| 162 | |
| 163 | if (!oprom->pcir_offset || !oprom->vbt_offset) { |
| 164 | rdev_munmap(&rd, (void *)oprom); |
| 165 | return CB_ERR; |
| 166 | } |
| 167 | |
| 168 | pcir = rdev_mmap(&rd, oprom->pcir_offset, sizeof(*pcir)); |
| 169 | if (pcir == NULL) { |
| 170 | rdev_munmap(&rd, (void *)oprom); |
| 171 | return CB_ERR; |
| 172 | } |
| 173 | |
| 174 | printk(BIOS_DEBUG, "GMA: locate_vbt_vbios: %x %x %x %x %x\n", |
| 175 | oprom->signature, pcir->vendor, pcir->classcode[0], |
| 176 | pcir->classcode[1], pcir->classcode[2]); |
| 177 | |
| 178 | /* Make sure we got an Intel VGA option rom */ |
| 179 | if ((oprom->signature != OPROM_SIGNATURE) || |
| 180 | (pcir->vendor != PCI_VENDOR_ID_INTEL) || |
| 181 | (pcir->signature != 0x52494350) || |
| 182 | (pcir->classcode[0] != 0x00) || |
| 183 | (pcir->classcode[1] != 0x00) || |
| 184 | (pcir->classcode[2] != 0x03)) { |
| 185 | rdev_munmap(&rd, (void *)oprom); |
| 186 | rdev_munmap(&rd, (void *)pcir); |
| 187 | return CB_ERR; |
| 188 | } |
| 189 | |
| 190 | rdev_munmap(&rd, (void *)pcir); |
| 191 | |
| 192 | /* Search for $VBT as some VBIOS are broken... */ |
| 193 | offset = oprom->vbt_offset; |
| 194 | do { |
| 195 | ret = rdev_chain(rdev, &rd, offset, |
| 196 | (opromsize * 512) - offset); |
| 197 | offset++; |
| 198 | } while (ret == CB_SUCCESS && vbt_validate(rdev) != CB_SUCCESS); |
| 199 | |
| 200 | offset--; |
| 201 | |
| 202 | if (ret == CB_SUCCESS && offset != oprom->vbt_offset) |
| 203 | printk(BIOS_WARNING, "GMA: Buggy VBIOS found\n"); |
| 204 | else if (ret != CB_SUCCESS) |
| 205 | printk(BIOS_ERR, "GMA: Broken VBIOS found\n"); |
| 206 | |
| 207 | rdev_munmap(&rd, (void *)oprom); |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | static enum cb_err locate_vbt_cbfs(struct region_device *rdev) |
| 212 | { |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 213 | size_t vbt_data_size; |
| 214 | void *vbt = locate_vbt(&vbt_data_size); |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 215 | |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 216 | if (vbt == NULL) |
| 217 | return CB_ERR; |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 218 | |
Patrick Georgi | 4a3956d | 2018-05-03 19:15:13 +0200 | [diff] [blame] | 219 | if (rdev_chain(rdev, &addrspace_32bit.rdev, (uintptr_t)vbt, |
| 220 | vbt_data_size)) |
| 221 | return CB_ERR; |
| 222 | |
| 223 | printk(BIOS_INFO, "GMA: Found VBT in CBFS\n"); |
| 224 | |
| 225 | return CB_SUCCESS; |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static enum cb_err locate_vbt_vbios_cbfs(struct region_device *rdev) |
| 229 | { |
| 230 | const u8 *oprom = |
| 231 | (const u8 *)pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2, 0))); |
| 232 | if (oprom == NULL) |
| 233 | return CB_ERR; |
| 234 | |
| 235 | printk(BIOS_INFO, "GMA: Found VBIOS in CBFS\n"); |
| 236 | |
| 237 | return locate_vbt_vbios(oprom, rdev); |
| 238 | } |
| 239 | |
| 240 | /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ |
| 241 | enum cb_err |
| 242 | intel_gma_init_igd_opregion(igd_opregion_t *opregion) |
| 243 | { |
| 244 | struct region_device rdev; |
| 245 | optionrom_vbt_t *vbt = NULL; |
| 246 | optionrom_vbt_t *ext_vbt; |
| 247 | bool found = false; |
| 248 | |
| 249 | /* Search for vbt.bin in CBFS. */ |
| 250 | if (locate_vbt_cbfs(&rdev) == CB_SUCCESS && |
| 251 | vbt_validate(&rdev) == CB_SUCCESS) { |
| 252 | found = true; |
| 253 | printk(BIOS_INFO, "GMA: Found valid VBT in CBFS\n"); |
| 254 | } |
| 255 | /* Search for pci8086,XXXX.rom in CBFS. */ |
| 256 | else if (locate_vbt_vbios_cbfs(&rdev) == CB_SUCCESS && |
| 257 | vbt_validate(&rdev) == CB_SUCCESS) { |
| 258 | found = true; |
| 259 | printk(BIOS_INFO, "GMA: Found valid VBT in VBIOS\n"); |
| 260 | } |
| 261 | /* |
| 262 | * Try to locate Intel VBIOS at 0xc0000. It might have been placed by |
| 263 | * Native Graphics Init as fake Option ROM or when coreboot did run the |
| 264 | * VBIOS on legacy platforms. |
| 265 | * TODO: Place generated fake VBT in CBMEM and get rid of this. |
| 266 | */ |
| 267 | else if (locate_vbt_vbios((u8 *)0xc0000, &rdev) == CB_SUCCESS && |
| 268 | vbt_validate(&rdev) == CB_SUCCESS) { |
| 269 | found = true; |
| 270 | printk(BIOS_INFO, "GMA: Found valid VBT in legacy area\n"); |
| 271 | } |
| 272 | |
| 273 | if (!found) { |
| 274 | printk(BIOS_ERR, "GMA: VBT couldn't be found\n"); |
| 275 | return CB_ERR; |
| 276 | } |
| 277 | |
| 278 | vbt = rdev_mmap_full(&rdev); |
| 279 | if (!vbt) { |
| 280 | printk(BIOS_ERR, "GMA: Error mapping VBT\n"); |
| 281 | return CB_ERR; |
| 282 | } |
| 283 | |
| 284 | if (vbt->hdr_vbt_size > region_device_sz(&rdev)) { |
| 285 | printk(BIOS_ERR, "GMA: Error mapped only a partial VBT\n"); |
| 286 | rdev_munmap(&rdev, vbt); |
| 287 | return CB_ERR; |
| 288 | } |
| 289 | |
| 290 | memset(opregion, 0, sizeof(igd_opregion_t)); |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 291 | |
| 292 | memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, |
| 293 | sizeof(opregion->header.signature)); |
Matt DeVillier | 53e4195 | 2017-06-27 13:07:43 -0500 | [diff] [blame] | 294 | memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, |
| 295 | ARRAY_SIZE(vbt->coreblock_biosbuild)); |
| 296 | /* Extended VBT support */ |
| 297 | if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { |
| 298 | ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); |
| 299 | |
| 300 | if (ext_vbt == NULL) { |
| 301 | printk(BIOS_ERR, |
| 302 | "GMA: Unable to add Ext VBT to cbmem!\n"); |
| 303 | rdev_munmap(&rdev, vbt); |
| 304 | return CB_ERR; |
| 305 | } |
| 306 | |
| 307 | memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); |
| 308 | opregion->mailbox3.rvda = (uintptr_t)ext_vbt; |
| 309 | opregion->mailbox3.rvds = vbt->hdr_vbt_size; |
| 310 | } else { |
| 311 | /* Raw VBT size which can fit in gvd1 */ |
| 312 | memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); |
| 313 | } |
| 314 | |
| 315 | rdev_munmap(&rdev, vbt); |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 316 | |
| 317 | /* 8kb */ |
| 318 | opregion->header.size = sizeof(igd_opregion_t) / 1024; |
Matt DeVillier | fd0a891 | 2017-10-19 22:44:18 -0500 | [diff] [blame] | 319 | |
| 320 | /* |
| 321 | * Left-shift version field to accomodate Intel Windows driver quirk |
| 322 | * when not using a VBIOS. |
| 323 | * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. |
| 324 | * |
| 325 | * Tested on: (platform, GPU, windows driver version) |
| 326 | * samsung/stumpy (SNB, GT2, 9.17.10.4459) |
| 327 | * google/link (IVB, GT2, 15.33.4653) |
| 328 | * google/wolf (HSW, GT1, 15.40.36.4703) |
| 329 | * google/panther (HSW, GT2, 15.40.36.4703) |
| 330 | * google/rikku (BDW, GT1, 15.40.36.4703) |
| 331 | * google/lulu (BDW, GT2, 15.40.36.4703) |
| 332 | * google/chell (SKL-Y, GT2, 15.45.21.4821) |
| 333 | * google/sentry (SKL-U, GT1, 15.45.21.4821) |
| 334 | * purism/librem13v2 (SKL-U, GT2, 15.45.21.4821) |
| 335 | * |
| 336 | * No adverse effects when using VBIOS or booting Linux. |
| 337 | */ |
| 338 | opregion->header.version = IGD_OPREGION_VERSION << 24; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 339 | |
| 340 | // FIXME We just assume we're mobile for now |
| 341 | opregion->header.mailboxes = MAILBOXES_MOBILE; |
| 342 | |
| 343 | // TODO Initialize Mailbox 1 |
Patrick Georgi | 0f68b23 | 2018-01-25 18:23:15 +0100 | [diff] [blame] | 344 | opregion->mailbox1.clid = 1; |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 345 | |
| 346 | // TODO Initialize Mailbox 3 |
| 347 | opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; |
| 348 | opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; |
| 349 | opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e |
| 350 | opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; |
| 351 | opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; |
| 352 | opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; |
| 353 | opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; |
| 354 | opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; |
| 355 | opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; |
| 356 | opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; |
| 357 | opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; |
| 358 | opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; |
| 359 | opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; |
| 360 | opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; |
| 361 | opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; |
| 362 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 363 | /* Write ASLS PCI register and prepare SWSCI register. */ |
| 364 | intel_gma_opregion_register((uintptr_t)opregion); |
| 365 | |
| 366 | return CB_SUCCESS; |
| 367 | } |