Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 17 | /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ |
Stefan Reinauer | 5e32823 | 2010-03-29 19:19:16 +0000 | [diff] [blame] | 18 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <string.h> |
| 21 | #include <arch/io.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 22 | #include <device/pci_def.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 23 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 24 | #include <arch/acpi.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 8a7d34b | 2010-02-22 09:15:13 +0000 | [diff] [blame] | 26 | #include <console/console.h> |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 27 | #include <cpu/x86/bist.h> |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 28 | #include <cpu/intel/romstage.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 29 | #include <halt.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/i945/i945.h> |
| 31 | #include <northbridge/intel/i945/raminit.h> |
| 32 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 33 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 34 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 35 | static void ich7_enable_lpc(void) |
| 36 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 37 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 38 | if (read_option(lpt, 0) != 0) |
| 39 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 40 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 41 | /* Enable Serial IRQ */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 42 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 43 | /* decode range */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 44 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 45 | /* decode range */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 46 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN |
| 47 | | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN |
| 48 | | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN); |
| 49 | /* COM3 and COM4 decode? */ |
| 50 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1); |
| 51 | /* ??decode?? */ |
| 52 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); |
| 53 | /* EC decode? */ |
| 54 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 55 | } |
| 56 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 57 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 58 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 59 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 60 | * but safe anyways" method. |
| 61 | */ |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 62 | static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 63 | { |
| 64 | unsigned int port = dev >> 8; |
| 65 | outb(0x55, port); |
| 66 | } |
| 67 | |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 68 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 69 | { |
| 70 | unsigned int port = dev >> 8; |
| 71 | outb(0xaa, port); |
| 72 | } |
| 73 | |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 74 | static void pnp_write_register(pnp_devfn_t dev, int reg, int val) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 75 | { |
| 76 | unsigned int port = dev >> 8; |
| 77 | outb(reg, port); |
| 78 | outb(val, port+1); |
| 79 | } |
| 80 | |
| 81 | static void early_superio_config(void) |
| 82 | { |
Antonello Dettori | 63028fd | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 83 | pnp_devfn_t dev; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 84 | |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 85 | dev = PNP_DEV(0x2e, 0x00); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 86 | |
| 87 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 88 | pnp_write_register(dev, 0x01, 0x94); /* Extended Parport modes */ |
| 89 | pnp_write_register(dev, 0x02, 0x88); /* UART power on */ |
| 90 | pnp_write_register(dev, 0x03, 0x72); /* Floppy */ |
| 91 | pnp_write_register(dev, 0x04, 0x01); /* EPP + SPP */ |
| 92 | pnp_write_register(dev, 0x14, 0x03); /* Floppy */ |
| 93 | pnp_write_register(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ |
| 94 | pnp_write_register(dev, 0x23, (0x378 >> 2)); /* PP base */ |
| 95 | pnp_write_register(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ |
| 96 | pnp_write_register(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ |
| 97 | pnp_write_register(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ |
| 98 | pnp_write_register(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ |
| 99 | pnp_write_register(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 100 | /* These are the SMI status registers in the SIO: */ |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 101 | pnp_write_register(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 102 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 103 | pnp_write_register(dev, 0x31, 0x00); /* GPIO1 DIR */ |
| 104 | pnp_write_register(dev, 0x32, 0x00); /* GPIO1 POL */ |
| 105 | pnp_write_register(dev, 0x33, 0x40); /* GPIO2 DIR */ |
| 106 | pnp_write_register(dev, 0x34, 0x00); /* GPIO2 POL */ |
| 107 | pnp_write_register(dev, 0x35, 0xff); /* GPIO3 DIR */ |
| 108 | pnp_write_register(dev, 0x36, 0x00); /* GPIO3 POL */ |
| 109 | pnp_write_register(dev, 0x37, 0xe0); /* GPIO4 DIR */ |
| 110 | pnp_write_register(dev, 0x38, 0x00); /* GPIO4 POL */ |
| 111 | pnp_write_register(dev, 0x39, 0x80); /* GPIO4 POL */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 112 | |
| 113 | pnp_exit_ext_func_mode(dev); |
| 114 | } |
| 115 | |
| 116 | static void rcba_config(void) |
| 117 | { |
| 118 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 119 | |
| 120 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 121 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 122 | |
| 123 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 124 | RCBA16(D31IR) = 0x0232; |
| 125 | RCBA16(D30IR) = 0x3246; |
| 126 | RCBA16(D29IR) = 0x0237; |
| 127 | RCBA16(D28IR) = 0x3201; |
| 128 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 129 | |
| 130 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 131 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 132 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 133 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 134 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 135 | |
| 136 | /* This should probably go into the ACPI OS Init trap */ |
| 137 | |
| 138 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 139 | RCBA32(0x1e84) = 0x00020001; |
| 140 | RCBA32(0x1e80) = 0x0000fe01; |
| 141 | |
| 142 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 143 | RCBA32(0x1e9c) = 0x000200f0; |
| 144 | RCBA32(0x1e98) = 0x000c0801; |
| 145 | } |
| 146 | |
| 147 | static void early_ich7_init(void) |
| 148 | { |
| 149 | uint8_t reg8; |
| 150 | uint32_t reg32; |
| 151 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 152 | /* program secondary mlt XXX byte? */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 153 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 154 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 155 | /* reset rtc power status */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 156 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 157 | reg8 &= ~(1 << 2); |
| 158 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 159 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 160 | /* usb transient disconnect */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 161 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 162 | reg8 |= (3 << 0); |
| 163 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 164 | |
| 165 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 166 | reg32 |= (1 << 29) | (1 << 17); |
| 167 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 168 | |
| 169 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 170 | reg32 |= (1 << 31) | (1 << 27); |
| 171 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 172 | |
| 173 | RCBA32(0x0088) = 0x0011d000; |
| 174 | RCBA16(0x01fc) = 0x060f; |
| 175 | RCBA32(0x01f4) = 0x86000040; |
| 176 | RCBA32(0x0214) = 0x10030549; |
| 177 | RCBA32(0x0218) = 0x00020504; |
| 178 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 179 | reg32 = RCBA32(GCS); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 180 | reg32 |= (1 << 6); |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 181 | RCBA32(GCS) = reg32; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 182 | reg32 = RCBA32(0x3430); |
| 183 | reg32 &= ~(3 << 0); |
| 184 | reg32 |= (1 << 0); |
| 185 | RCBA32(0x3430) = reg32; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 186 | RCBA16(0x0200) = 0x2008; |
| 187 | RCBA8(0x2027) = 0x0d; |
| 188 | RCBA16(0x3e08) |= (1 << 7); |
| 189 | RCBA16(0x3e48) |= (1 << 7); |
| 190 | RCBA32(0x3e0e) |= (1 << 7); |
| 191 | RCBA32(0x3e4e) |= (1 << 7); |
| 192 | |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 193 | /* next step only on ich7m b0 and later: */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 194 | reg32 = RCBA32(0x2034); |
| 195 | reg32 &= ~(0x0f << 16); |
| 196 | reg32 |= (5 << 16); |
| 197 | RCBA32(0x2034) = reg32; |
| 198 | } |
| 199 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 200 | static void init_artec_dongle(void) |
| 201 | { |
Elyes HAOUAS | ec16e93 | 2016-10-07 18:22:44 +0200 | [diff] [blame] | 202 | /* Enable 4MB decoding */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 203 | outb(0xf1, 0x88); |
| 204 | outb(0xf4, 0x88); |
| 205 | } |
| 206 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 207 | void mainboard_romstage_entry(unsigned long bist) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 208 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 209 | int s3resume = 0; |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 210 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 211 | if (bist == 0) |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 212 | enable_lapic(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 213 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 214 | /* Force PCIRST# */ |
| 215 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 216 | udelay(200 * 1000); |
| 217 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 218 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 219 | ich7_enable_lpc(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 220 | early_superio_config(); |
| 221 | |
| 222 | /* Set up the console */ |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 223 | console_init(); |
| 224 | |
| 225 | /* Halt if there was a built in self test failure */ |
| 226 | report_bist_failure(bist); |
| 227 | |
| 228 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 229 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 230 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 231 | halt(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | /* Perform some early chipset initialization required |
| 235 | * before RAM initialization can work |
| 236 | */ |
| 237 | i945_early_initialization(); |
| 238 | |
| 239 | /* This has to happen after i945_early_initialization() */ |
| 240 | init_artec_dongle(); |
| 241 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 242 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 243 | |
| 244 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 245 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 246 | |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 247 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 248 | dump_spd_registers(); |
| 249 | #endif |
| 250 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 251 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 252 | |
| 253 | /* Perform some initialization that must run before stage2 */ |
| 254 | early_ich7_init(); |
| 255 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 256 | /* This should probably go away. Until now it is required |
| 257 | * and mainboard specific |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 258 | */ |
| 259 | rcba_config(); |
| 260 | |
| 261 | /* Chipset Errata! */ |
| 262 | fixup_i945_errata(); |
| 263 | |
| 264 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 265 | i945_late_initialization(s3resume); |
Stefan Reinauer | 838c5a5 | 2010-01-17 14:08:17 +0000 | [diff] [blame] | 266 | } |