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Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth5c354b92019-04-22 14:55:16 -06002
Felix Helddd2f3fa2021-02-08 22:23:54 +01003#include <amdblocks/cpu.h>
Felix Heldf1093af2021-07-13 23:00:26 +02004#include <amdblocks/mca.h>
Zheng Bao6ba591b2020-06-09 09:47:06 +08005#include <cpu/amd/microcode.h>
Arthur Heymans615818f2022-05-31 21:33:43 +02006#include <cpu/cpu.h>
Arthur Heymans615818f2022-05-31 21:33:43 +02007#include <device/device.h>
Arthur Heymans615818f2022-05-31 21:33:43 +02008#include <soc/cpu.h>
Martin Roth5c354b92019-04-22 14:55:16 -06009
Felix Heldf142ba52021-04-22 18:26:43 +020010_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
11 "available cores, use the downcore_mode and disable_smt devicetree settings instead.");
12
Marshall Dawson34c30562019-07-16 15:18:00 -060013static void model_17_init(struct device *dev)
Martin Roth5c354b92019-04-22 14:55:16 -060014{
15 check_mca();
Chris Wange2497d02020-08-03 22:36:13 +080016 set_cstate_io_addr();
Zheng Bao6ba591b2020-06-09 09:47:06 +080017
Grzegorz Bernackid34dbe52023-04-25 15:30:14 +000018 amd_apply_microcode_patch();
Martin Roth5c354b92019-04-22 14:55:16 -060019}
20
21static struct device_operations cpu_dev_ops = {
Marshall Dawson34c30562019-07-16 15:18:00 -060022 .init = model_17_init,
Martin Roth5c354b92019-04-22 14:55:16 -060023};
24
25static struct cpu_device_id cpu_table[] = {
Felix Heldcf9b0692023-02-06 17:04:54 +010026 { X86_VENDOR_AMD, RAVEN1_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
27 { X86_VENDOR_AMD, PICASSO_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
28 { X86_VENDOR_AMD, RAVEN2_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
Felix Held1e781652023-02-08 11:39:16 +010029 CPU_TABLE_END
Martin Roth5c354b92019-04-22 14:55:16 -060030};
31
Marshall Dawson34c30562019-07-16 15:18:00 -060032static const struct cpu_driver model_17 __cpu_driver = {
Martin Roth5c354b92019-04-22 14:55:16 -060033 .ops = &cpu_dev_ops,
34 .id_table = cpu_table,
35};