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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / southbridge / intel / i82801gx / ide.c
blob: 71fc738632f8b63e8f54058e86a90ca5c1e38595 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]2
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +0200[diff] [blame]6#include <device/pci_ops.h>
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]7#include <device/pci_ids.h>
Arthur Heymans742df5a2019-06-03 16:24:41 +0200[diff] [blame]8#include "chip.h"
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]9#include "i82801gx.h"
10
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]11static void ide_init(struct device *dev)
12{
13 u16 ideTimingConfig;
14 u32 reg32;
Stefan Reinauera8e11682009-03-11 14:54:18 +0000[diff] [blame]15 u32 enable_primary, enable_secondary;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]16
17 /* Get the chip configuration */
Elyes HAOUAS8d9a6f12020-04-28 04:57:27 +0200[diff] [blame]18 const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]19
Paul Menzel7f1df8c2015-10-11 15:48:36 +0200[diff] [blame]20 printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
Stefan Reinauera8e11682009-03-11 14:54:18 +0000[diff] [blame]21 if (config == NULL) {
Uwe Hermann607614d2010-11-18 20:12:13 +0000[diff] [blame]22 printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]23 // Trying to set somewhat safe defaults instead of bailing out.
Stefan Reinauera8e11682009-03-11 14:54:18 +0000[diff] [blame]24 enable_primary = enable_secondary = 1;
25 } else {
26 enable_primary = config->ide_enable_primary;
27 enable_secondary = config->ide_enable_secondary;
28 }
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]29
Elyes HAOUAS12349252020-04-27 05:08:26 +0200[diff] [blame]30 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]31
32 /* Native Capable, but not enabled. */
33 pci_write_config8(dev, 0x09, 0x8a);
34
35 ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
36 ideTimingConfig &= ~IDE_DECODE_ENABLE;
37 ideTimingConfig |= IDE_SITRE;
38 if (enable_primary) {
39 /* Enable primary IDE interface. */
40 ideTimingConfig |= IDE_DECODE_ENABLE;
Elyes HAOUASae22fe22020-05-21 09:04:16 +0200[diff] [blame]41 ideTimingConfig |= IDE_ISP_3_CLOCKS;
42 ideTimingConfig |= IDE_RCT_1_CLOCKS;
43 ideTimingConfig |= IDE_IE0;
44 ideTimingConfig |= IDE_TIME0; // TIME0
Paul Menzel7f1df8c2015-10-11 15:48:36 +0200[diff] [blame]45 printk(BIOS_DEBUG, " IDE0");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]46 }
47 pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
48
49 ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
50 ideTimingConfig &= ~IDE_DECODE_ENABLE;
51 ideTimingConfig |= IDE_SITRE;
52 if (enable_secondary) {
53 /* Enable secondary IDE interface. */
54 ideTimingConfig |= IDE_DECODE_ENABLE;
Elyes HAOUASae22fe22020-05-21 09:04:16 +0200[diff] [blame]55 ideTimingConfig |= IDE_ISP_3_CLOCKS;
56 ideTimingConfig |= IDE_RCT_1_CLOCKS;
57 ideTimingConfig |= IDE_IE0;
58 ideTimingConfig |= IDE_TIME0;
Paul Menzel7f1df8c2015-10-11 15:48:36 +0200[diff] [blame]59 printk(BIOS_DEBUG, " IDE1");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]60 }
61 pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
62
63 /* Set IDE I/O Configuration */
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]64 reg32 = 0;
65 /* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
66 if (enable_primary)
67 reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]68 if (enable_secondary)
Stefan Reinaueraca6ec62009-10-26 17:12:21 +0000[diff] [blame]69 reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]70 pci_write_config32(dev, IDE_CONFIG, reg32);
71
72 /* Set Interrupt Line */
73 /* Interrupt Pin is set by D31IP.PIP */
74 pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
Stefan Reinauera8e11682009-03-11 14:54:18 +0000[diff] [blame]75
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]76 printk(BIOS_DEBUG, "\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]77}
78
79static struct device_operations ide_ops = {
80 .read_resources = pci_dev_read_resources,
81 .set_resources = pci_dev_set_resources,
82 .enable_resources = pci_dev_enable_resources,
83 .init = ide_init,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]84 .enable = i82801gx_enable,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200[diff] [blame]85 .ops_pci = &pci_dev_ops_pci,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]86};
87
Uwe Hermannbddc6932008-10-29 13:51:31 +0000[diff] [blame]88/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]89static const struct pci_driver i82801gx_ide __pci_driver = {
90 .ops = &ide_ops,
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]91 .vendor = PCI_VID_INTEL,
Uwe Hermann5d7a1c82008-10-31 18:41:09 +0000[diff] [blame]92 .device = 0x27df,
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame]93};