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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / southbridge / intel / i82371eb / early_pm.c
blob: 2a1c6ebae9140f6e60cc9cbc2cd63821d6aa9435 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]2
3#include <stdint.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +0200[diff] [blame]4#include <device/pci_ops.h>
Kyösti Mälkki8a41f4b2019-02-08 18:14:34 +0200[diff] [blame]5#include <device/pci.h>
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]6#include <device/pci_def.h>
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]7#include <device/pci_ids.h>
8#include "i82371eb.h"
9
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]10void enable_pm(void)
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]11{
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]12 u8 reg8;
13 u16 reg16;
14
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]15 /* Get the SMBus/PM device of the 82371AB/EB/MB. */
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]16 const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VID_INTEL,
17 PCI_DID_INTEL_82371AB_SMB_ACPI), 0);
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]18
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]19 /* Set the PM I/O base. */
Tobias Diedriche87c38e2010-11-27 09:40:16 +0000[diff] [blame]20 pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]21
22 /* Enable access to the PM I/O space. */
23 reg16 = pci_read_config16(dev, PCI_COMMAND);
24 reg16 |= PCI_COMMAND_IO;
25 pci_write_config16(dev, PCI_COMMAND, reg16);
26
27 /* PM I/O Space Enable (PMIOSE). */
28 reg8 = pci_read_config8(dev, PMREGMISC);
29 reg8 |= PMIOSE;
30 pci_write_config8(dev, PMREGMISC, reg8);
31}