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review.coreboot.org / coreboot / ac9590395e0404e1fa1199643a1b28b228f992e5 / . / src / southbridge / intel / i82371eb / early_pm.c
blob: 8da73698c94c536b00dbc4eba036579e2286e2b3 [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +0200[diff] [blame]1/* This file is part of the coreboot project. */
Patrick Georgiac959032020-05-05 22:49:26 +0200[diff] [blame^]2/* SPDX-License-Identifier: GPL-2.0-or-later */
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]3
4#include <stdint.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +0200[diff] [blame]5#include <device/pci_ops.h>
Kyösti Mälkki8a41f4b2019-02-08 18:14:34 +0200[diff] [blame]6#include <device/pci.h>
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]7#include <device/pci_def.h>
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]8#include <device/pci_ids.h>
9#include "i82371eb.h"
10
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]11void enable_pm(void)
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]12{
Antonello Dettorif068a732016-09-03 10:45:33 +0200[diff] [blame]13 pci_devfn_t dev;
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]14 u8 reg8;
15 u16 reg16;
16
Uwe Hermann115c5b92010-10-09 17:00:18 +0000[diff] [blame]17 /* Get the SMBus/PM device of the 82371AB/EB/MB. */
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]18 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
19 PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
20
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]21 /* Set the PM I/O base. */
Tobias Diedriche87c38e2010-11-27 09:40:16 +0000[diff] [blame]22 pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
Uwe Hermann0865b4d2010-09-19 21:12:05 +0000[diff] [blame]23
24 /* Enable access to the PM I/O space. */
25 reg16 = pci_read_config16(dev, PCI_COMMAND);
26 reg16 |= PCI_COMMAND_IO;
27 pci_write_config16(dev, PCI_COMMAND, reg16);
28
29 /* PM I/O Space Enable (PMIOSE). */
30 reg8 = pci_read_config8(dev, PMREGMISC);
31 reg8 |= PMIOSE;
32 pci_write_config8(dev, PMREGMISC, reg8);
33}