Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | #include <console/console.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 4 | #include <commonlib/console/post_codes.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 5 | #include <device/mmio.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci_ops.h> |
Srinidhi N Kaushik | 876b422 | 2020-12-02 17:14:32 -0800 | [diff] [blame] | 8 | #include <intelblocks/dmi.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 9 | #include <intelblocks/fast_spi.h> |
| 10 | #include <intelblocks/gspi.h> |
| 11 | #include <intelblocks/lpc_lib.h> |
| 12 | #include <intelblocks/p2sb.h> |
| 13 | #include <intelblocks/pcr.h> |
| 14 | #include <intelblocks/pmclib.h> |
| 15 | #include <intelblocks/rtc.h> |
| 16 | #include <soc/bootblock.h> |
| 17 | #include <soc/espi.h> |
| 18 | #include <soc/iomap.h> |
| 19 | #include <soc/p2sb.h> |
| 20 | #include <soc/pch.h> |
| 21 | #include <soc/pci_devs.h> |
| 22 | #include <soc/pcr_ids.h> |
| 23 | #include <soc/pm.h> |
| 24 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 25 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00 |
| 26 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 27 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 28 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 29 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 30 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 31 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 32 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 33 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 34 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 35 | #define PCR_DMI_ACPIBA 0x27B4 |
| 36 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 37 | #define PCR_DMI_PMBASEA 0x27AC |
| 38 | #define PCR_DMI_PMBASEC 0x27B0 |
| 39 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 40 | static void soc_config_pwrmbase(void) |
| 41 | { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 42 | /* |
| 43 | * Assign Resources to PWRMBASE |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 44 | * Clear BIT 1-2 Command Register |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 45 | */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 46 | pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 47 | |
| 48 | /* Program PWRM Base */ |
| 49 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 50 | |
| 51 | /* Enable Bus Master and MMIO Space */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 52 | pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 53 | |
| 54 | /* Enable PWRM in PMC */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 55 | setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | void bootblock_pch_early_init(void) |
| 59 | { |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 60 | /* |
| 61 | * Perform P2SB configuration before any another controller initialization as the |
| 62 | * controller might want to perform PCR settings. |
| 63 | */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 64 | p2sb_enable_bar(); |
| 65 | p2sb_configure_hpet(); |
| 66 | |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 67 | fast_spi_early_init(SPI_BASE_ADDRESS); |
| 68 | gspi_early_bar_init(); |
| 69 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 70 | /* |
| 71 | * Enabling PWRM Base for accessing |
| 72 | * Global Reset Cause Register. |
| 73 | */ |
| 74 | soc_config_pwrmbase(); |
| 75 | } |
| 76 | |
| 77 | static void soc_config_acpibase(void) |
| 78 | { |
| 79 | uint32_t pmc_reg_value; |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 80 | uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 81 | |
| 82 | pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); |
| 83 | |
| 84 | if (pmc_reg_value != 0xffffffff) { |
| 85 | /* Disable Io Space before changing the address */ |
| 86 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
| 87 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 88 | /* Program ABASE in PSF3 PMC space BAR4*/ |
| 89 | pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, |
| 90 | ACPI_BASE_ADDRESS); |
| 91 | /* Enable IO Space */ |
| 92 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
| 93 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 94 | } |
| 95 | } |
| 96 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 97 | void pch_early_iorange_init(void) |
| 98 | { |
| 99 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 100 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
| 101 | |
| 102 | /* IO Decode Range */ |
| 103 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 104 | lpc_io_setup_comm_a_b(); |
| 105 | |
| 106 | /* IO Decode Enable */ |
Michael Niewöhner | 33c0aac | 2021-01-24 12:56:12 +0100 | [diff] [blame] | 107 | lpc_enable_fixed_io_ranges(io_enables); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 108 | |
| 109 | /* Program generic IO Decode Range */ |
| 110 | pch_enable_lpc(); |
| 111 | } |
| 112 | |
Usha P | 253b7d2 | 2020-07-15 14:14:36 +0530 | [diff] [blame] | 113 | void bootblock_pch_init(void) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 114 | { |
| 115 | /* |
| 116 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 117 | * GPE0_STS, GPE0_EN registers. |
| 118 | */ |
| 119 | soc_config_acpibase(); |
| 120 | |
| 121 | /* Set up GPE configuration */ |
| 122 | pmc_gpe_init(); |
| 123 | |
| 124 | enable_rtc_upper_bank(); |
| 125 | } |