Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <console/post_codes.h> |
| 5 | #include <device/mmio.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <intelblocks/fast_spi.h> |
| 9 | #include <intelblocks/gspi.h> |
| 10 | #include <intelblocks/lpc_lib.h> |
| 11 | #include <intelblocks/p2sb.h> |
| 12 | #include <intelblocks/pcr.h> |
| 13 | #include <intelblocks/pmclib.h> |
| 14 | #include <intelblocks/rtc.h> |
| 15 | #include <soc/bootblock.h> |
| 16 | #include <soc/espi.h> |
| 17 | #include <soc/iomap.h> |
| 18 | #include <soc/p2sb.h> |
| 19 | #include <soc/pch.h> |
| 20 | #include <soc/pci_devs.h> |
| 21 | #include <soc/pcr_ids.h> |
| 22 | #include <soc/pm.h> |
| 23 | |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 24 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00 |
| 25 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 26 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 27 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 28 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 29 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 30 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 31 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 32 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 33 | |
| 34 | #define PCR_DMI_DMICTL 0x2234 |
| 35 | #define PCR_DMI_DMICTL_SRLOCK (1 << 31) |
| 36 | |
| 37 | #define PCR_DMI_ACPIBA 0x27B4 |
| 38 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 39 | #define PCR_DMI_PMBASEA 0x27AC |
| 40 | #define PCR_DMI_PMBASEC 0x27B0 |
| 41 | |
| 42 | #define PCR_DMI_LPCIOD 0x2770 |
| 43 | #define PCR_DMI_LPCIOE 0x2774 |
| 44 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 45 | static void soc_config_pwrmbase(void) |
| 46 | { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 47 | /* |
| 48 | * Assign Resources to PWRMBASE |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 49 | * Clear BIT 1-2 Command Register |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 50 | */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 51 | pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 52 | |
| 53 | /* Program PWRM Base */ |
| 54 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 55 | |
| 56 | /* Enable Bus Master and MMIO Space */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 57 | pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 58 | |
| 59 | /* Enable PWRM in PMC */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 60 | setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | void bootblock_pch_early_init(void) |
| 64 | { |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame^] | 65 | /* |
| 66 | * Perform P2SB configuration before any another controller initialization as the |
| 67 | * controller might want to perform PCR settings. |
| 68 | */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 69 | p2sb_enable_bar(); |
| 70 | p2sb_configure_hpet(); |
| 71 | |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame^] | 72 | fast_spi_early_init(SPI_BASE_ADDRESS); |
| 73 | gspi_early_bar_init(); |
| 74 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 75 | /* |
| 76 | * Enabling PWRM Base for accessing |
| 77 | * Global Reset Cause Register. |
| 78 | */ |
| 79 | soc_config_pwrmbase(); |
| 80 | } |
| 81 | |
| 82 | static void soc_config_acpibase(void) |
| 83 | { |
| 84 | uint32_t pmc_reg_value; |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 85 | uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 86 | |
| 87 | pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); |
| 88 | |
| 89 | if (pmc_reg_value != 0xffffffff) { |
| 90 | /* Disable Io Space before changing the address */ |
| 91 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
| 92 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 93 | /* Program ABASE in PSF3 PMC space BAR4*/ |
| 94 | pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, |
| 95 | ACPI_BASE_ADDRESS); |
| 96 | /* Enable IO Space */ |
| 97 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
| 98 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | static int pch_check_decode_enable(void) |
| 103 | { |
| 104 | uint32_t dmi_control; |
| 105 | |
| 106 | /* |
| 107 | * This cycle decoding is only allowed to set when |
| 108 | * DMICTL.SRLOCK is 0. |
| 109 | */ |
| 110 | dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); |
| 111 | if (dmi_control & PCR_DMI_DMICTL_SRLOCK) |
| 112 | return -1; |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | void pch_early_iorange_init(void) |
| 117 | { |
| 118 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 119 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
| 120 | |
| 121 | /* IO Decode Range */ |
| 122 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 123 | lpc_io_setup_comm_a_b(); |
| 124 | |
| 125 | /* IO Decode Enable */ |
| 126 | if (pch_check_decode_enable() == 0) { |
| 127 | io_enables = lpc_enable_fixed_io_ranges(io_enables); |
| 128 | /* |
| 129 | * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same |
| 130 | * value programmed in ESPI PCI offset 82h. |
| 131 | */ |
| 132 | pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); |
| 133 | /* |
| 134 | * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same |
| 135 | * value programmed in LPC PCI offset 80h. |
| 136 | */ |
| 137 | pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); |
| 138 | } |
| 139 | |
| 140 | /* Program generic IO Decode Range */ |
| 141 | pch_enable_lpc(); |
| 142 | } |
| 143 | |
Usha P | 253b7d2 | 2020-07-15 14:14:36 +0530 | [diff] [blame] | 144 | void bootblock_pch_init(void) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 145 | { |
| 146 | /* |
| 147 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 148 | * GPE0_STS, GPE0_EN registers. |
| 149 | */ |
| 150 | soc_config_acpibase(); |
| 151 | |
| 152 | /* Set up GPE configuration */ |
| 153 | pmc_gpe_init(); |
| 154 | |
| 155 | enable_rtc_upper_bank(); |
| 156 | } |