blob: 64192695c6f20398e7cd3e2da348120c1a929f98 [file] [log] [blame]
Marshall Dawson6ab5ed32019-05-29 09:24:18 -06001config SOC_AMD_COMMON_BLOCK_LPC
2 bool
Marshall Dawson6ab5ed32019-05-29 09:24:18 -06003 help
4 Select this option to use the traditional LPC-ISA bridge at D14F3.
Raul E Rangel314c7162020-05-01 14:04:08 -06005
6config PROVIDES_ROM_SHARING
7 bool
Raul E Rangel314c7162020-05-01 14:04:08 -06008 help
9 Select this option if the LPC bridge supports ROM sharing.
Furquan Shaikhefe27cf2020-05-04 20:59:23 -070010
Raul E Rangel3ba21802021-06-24 17:03:35 -060011config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
12 bool
13 select X86_CUSTOM_BOOTMEDIA
Karthikeyan Ramasubramanian953f2ad2021-07-28 23:41:42 -060014 select SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
Raul E Rangeld373d5d2021-06-25 11:07:23 -060015 depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE
Raul E Rangel3ba21802021-06-24 17:03:35 -060016 help
17 Select this option to enable SPI DMA support.
18
Raul E Rangelc0025c22021-11-10 13:09:20 -070019# The LPC SPI DMA controller requires the source and destination to be 64 byte
Raul E Rangelcf17cd82021-07-23 16:43:18 -060020# aligned.
21config CBFS_CACHE_ALIGN
22 int
23 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
24
Raul E Rangelc0025c22021-11-10 13:09:20 -070025config FSP_ALIGNMENT_FSP_S
26 int
27 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
28
29config FSP_ALIGNMENT_FSP_M
30 int
31 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
32
Furquan Shaikhefe27cf2020-05-04 20:59:23 -070033config SOC_AMD_COMMON_BLOCK_HAS_ESPI
34 bool
Furquan Shaikhefe27cf2020-05-04 20:59:23 -070035 help
36 Select this option if platform supports eSPI using D14F3 configuration
37 registers.
38
39config SOC_AMD_COMMON_BLOCK_USE_ESPI
40 bool
41 depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
Furquan Shaikhefe27cf2020-05-04 20:59:23 -070042 help
43 Select this option if mainboard uses eSPI instead of LPC (if supported
44 by platform).