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review.coreboot.org / coreboot / cf17cd81d3e7f098fdef8d3af6f167409e1b157e / . / src / soc / amd / common / block / lpc / Kconfig
blob: 76f4ec7ac3abd1fa9071f4a0faf04b1211d5e68d [file] [log] [blame]
Marshall Dawson6ab5ed32019-05-29 09:24:18 -0600[diff] [blame]1config SOC_AMD_COMMON_BLOCK_LPC
2 bool
Marshall Dawson6ab5ed32019-05-29 09:24:18 -0600[diff] [blame]3 help
4 Select this option to use the traditional LPC-ISA bridge at D14F3.
Raul E Rangel314c7162020-05-01 14:04:08 -0600[diff] [blame]5
6config PROVIDES_ROM_SHARING
7 bool
Raul E Rangel314c7162020-05-01 14:04:08 -0600[diff] [blame]8 help
9 Select this option if the LPC bridge supports ROM sharing.
Furquan Shaikhefe27cf2020-05-04 20:59:23 -0700[diff] [blame]10
Raul E Rangel3ba21802021-06-24 17:03:35 -0600[diff] [blame]11config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
12 bool
13 select X86_CUSTOM_BOOTMEDIA
Karthikeyan Ramasubramanian953f2ad2021-07-28 23:41:42 -0600[diff] [blame]14 select SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
Raul E Rangeld373d5d2021-06-25 11:07:23 -0600[diff] [blame]15 depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE
Raul E Rangel3ba21802021-06-24 17:03:35 -0600[diff] [blame]16 help
17 Select this option to enable SPI DMA support.
18
Raul E Rangelcf17cd82021-07-23 16:43:18 -0600[diff] [blame^]19# The LPC SPI DMA controller requires the destination buffers to be 64 byte
20# aligned.
21config CBFS_CACHE_ALIGN
22 int
23 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
24
Furquan Shaikhefe27cf2020-05-04 20:59:23 -0700[diff] [blame]25config SOC_AMD_COMMON_BLOCK_HAS_ESPI
26 bool
Furquan Shaikhefe27cf2020-05-04 20:59:23 -0700[diff] [blame]27 help
28 Select this option if platform supports eSPI using D14F3 configuration
29 registers.
30
31config SOC_AMD_COMMON_BLOCK_USE_ESPI
32 bool
33 depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
Furquan Shaikhefe27cf2020-05-04 20:59:23 -0700[diff] [blame]34 help
35 Select this option if mainboard uses eSPI instead of LPC (if supported
36 by platform).