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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / mainboard / siemens / mc_apl1 / variants / mc_apl2 / mainboard.c
blob: 430e67e171044dd25a006b4bfb885f6742e52482 [file] [log] [blame]
Angel Pons6ad91762020-04-03 01:23:24 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]2
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]3#include <device/pci_def.h>
4#include <device/pci_ids.h>
5#include <device/pci_ops.h>
Elyes HAOUAS485a83f2021-02-01 21:36:53 +0100[diff] [blame]6#include <device/device.h>
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]7#include <baseboard/variants.h>
Werner Zeh42065f82019-05-02 12:45:21 +0200[diff] [blame]8
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]9void variant_mainboard_final(void)
10{
11 struct device *dev;
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]12
Werner Zehe8fc8f32021-07-22 06:44:01 +0200[diff] [blame]13 if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) {
Werner Zeh1412ffa2021-07-20 07:33:20 +0200[diff] [blame]14 /* Set Master Enable for on-board PCI device if allowed. */
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]15 dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0);
Werner Zeh1412ffa2021-07-20 07:33:20 +0200[diff] [blame]16 if (dev) {
17 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
18 }
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]19 }
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]20}