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review.coreboot.org / coreboot / 485a83f1f3bb88b7fac2a3434fb7dd266814a9b2 / . / src / mainboard / siemens / mc_apl1 / variants / mc_apl2 / mainboard.c
blob: 1baa8ec8025e5cd6cd3553bcaee465e27dbc1d9a [file] [log] [blame]
Angel Pons6ad91762020-04-03 01:23:24 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]2
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]3#include <device/pci_def.h>
4#include <device/pci_ids.h>
5#include <device/pci_ops.h>
Elyes HAOUAS485a83f2021-02-01 21:36:53 +0100[diff] [blame^]6#include <device/device.h>
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]7#include <baseboard/variants.h>
Werner Zeh42065f82019-05-02 12:45:21 +0200[diff] [blame]8
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]9void variant_mainboard_final(void)
10{
11 struct device *dev;
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]12
13 /* Set Master Enable for on-board PCI device. */
14 dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
15 if (dev) {
Angel Pons28ed7872020-11-10 20:07:33 +0100[diff] [blame]16 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]17 }
Mario Scheithauer66038c82018-09-25 17:26:32 +0200[diff] [blame]18}