Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _AMD_FW_TOOL_H_ |
| 4 | #define _AMD_FW_TOOL_H_ |
| 5 | |
Karthikeyan Ramasubramanian | 236245e | 2022-09-06 14:02:41 -0600 | [diff] [blame] | 6 | #include <commonlib/bsd/compiler.h> |
Elyes Haouas | 7d67a19 | 2022-10-14 09:58:29 +0200 | [diff] [blame] | 7 | #include <commonlib/bsd/helpers.h> |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 8 | #include <openssl/sha.h> |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 9 | #include <stdint.h> |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 10 | #include <stdbool.h> |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 11 | |
Zheng Bao | f080cd5 | 2023-03-22 12:50:36 +0800 | [diff] [blame] | 12 | #define ERASE_ALIGNMENT 0x1000U |
| 13 | #define TABLE_ALIGNMENT 0x1000U |
| 14 | #define BLOB_ALIGNMENT 0x100U |
| 15 | #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) |
| 16 | #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) |
| 17 | |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 18 | enum platform { |
| 19 | PLATFORM_UNKNOWN, |
| 20 | PLATFORM_CARRIZO, |
| 21 | PLATFORM_STONEYRIDGE, |
| 22 | PLATFORM_RAVEN, |
| 23 | PLATFORM_PICASSO, |
| 24 | PLATFORM_RENOIR, |
| 25 | PLATFORM_CEZANNE, |
| 26 | PLATFORM_MENDOCINO, |
| 27 | PLATFORM_LUCIENNE, |
| 28 | PLATFORM_PHOENIX, |
| 29 | PLATFORM_GLINDA |
| 30 | }; |
| 31 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 32 | typedef enum _amd_fw_type { |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 33 | AMD_FW_PSP_PUBKEY = 0x00, |
| 34 | AMD_FW_PSP_BOOTLOADER = 0x01, |
| 35 | AMD_FW_PSP_SECURED_OS = 0x02, |
| 36 | AMD_FW_PSP_RECOVERY = 0x03, |
| 37 | AMD_FW_PSP_NVRAM = 0x04, |
| 38 | AMD_FW_PSP_RTM_PUBKEY = 0x05, |
| 39 | AMD_FW_PSP_SMU_FIRMWARE = 0x08, |
| 40 | AMD_FW_PSP_SECURED_DEBUG = 0x09, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 41 | AMD_FW_ABL_PUBKEY = 0x0a, |
Arthur Heymans | aafbe13 | 2022-09-30 08:33:28 +0200 | [diff] [blame] | 42 | AMD_PSP_FUSE_CHAIN = 0x0b, |
| 43 | AMD_FW_PSP_TRUSTLETS = 0x0c, |
| 44 | AMD_FW_PSP_TRUSTLETKEY = 0x0d, |
| 45 | AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 46 | AMD_DEBUG_UNLOCK = 0x13, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 47 | AMD_BOOT_DRIVER = 0x1b, |
| 48 | AMD_SOC_DRIVER = 0x1c, |
| 49 | AMD_DEBUG_DRIVER = 0x1d, |
| 50 | AMD_INTERFACE_DRIVER = 0x1f, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 51 | AMD_HW_IPCFG = 0x20, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 52 | AMD_WRAPPED_IKEK = 0x21, |
| 53 | AMD_TOKEN_UNLOCK = 0x22, |
| 54 | AMD_SEC_GASKET = 0x24, |
| 55 | AMD_MP2_FW = 0x25, |
| 56 | AMD_DRIVER_ENTRIES = 0x28, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 57 | AMD_FW_KVM_IMAGE = 0x29, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 58 | AMD_FW_MP5 = 0x2a, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 59 | AMD_S0I3_DRIVER = 0x2d, |
| 60 | AMD_ABL0 = 0x30, |
| 61 | AMD_ABL1 = 0x31, |
| 62 | AMD_ABL2 = 0x32, |
| 63 | AMD_ABL3 = 0x33, |
| 64 | AMD_ABL4 = 0x34, |
| 65 | AMD_ABL5 = 0x35, |
| 66 | AMD_ABL6 = 0x36, |
| 67 | AMD_ABL7 = 0x37, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 68 | AMD_SEV_DATA = 0x38, |
| 69 | AMD_SEV_CODE = 0x39, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 70 | AMD_FW_PSP_WHITELIST = 0x3a, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 71 | AMD_VBIOS_BTLOADER = 0x3c, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 72 | AMD_FW_L2_PTR = 0x40, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 73 | AMD_FW_DXIO = 0x42, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 74 | AMD_FW_USB_PHY = 0x44, |
| 75 | AMD_FW_TOS_SEC_POLICY = 0x45, |
| 76 | AMD_FW_DRTM_TA = 0x47, |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 77 | AMD_FW_RECOVERYAB_A = 0x48, |
| 78 | AMD_FW_RECOVERYAB_B = 0x4A, |
| 79 | AMD_FW_BIOS_TABLE = 0x49, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 80 | AMD_FW_KEYDB_BL = 0x50, |
| 81 | AMD_FW_KEYDB_TOS = 0x51, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 82 | AMD_FW_PSP_VERSTAGE = 0x52, |
| 83 | AMD_FW_VERSTAGE_SIG = 0x53, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 84 | AMD_RPMC_NVRAM = 0x54, |
Zheng Bao | ab84fd7 | 2022-01-27 22:38:27 +0800 | [diff] [blame] | 85 | AMD_FW_SPL = 0x55, |
Zheng Bao | bf29a0d | 2020-12-03 23:00:48 +0800 | [diff] [blame] | 86 | AMD_FW_DMCU_ERAM = 0x58, |
| 87 | AMD_FW_DMCU_ISR = 0x59, |
Felix Held | 5f18bb7 | 2022-03-24 02:04:51 +0100 | [diff] [blame] | 88 | AMD_FW_MSMU = 0x5a, |
| 89 | AMD_FW_SPIROM_CFG = 0x5c, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 90 | AMD_FW_MPIO = 0x5d, |
Felix Held | 9f5a5ee | 2023-02-01 19:21:11 +0100 | [diff] [blame] | 91 | AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ |
| 92 | AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ |
Felix Held | 5f18bb7 | 2022-03-24 02:04:51 +0100 | [diff] [blame] | 93 | AMD_FW_DMCUB = 0x71, |
Zheng Bao | b993cb2 | 2021-02-02 18:48:23 +0800 | [diff] [blame] | 94 | AMD_FW_PSP_BOOTLOADER_AB = 0x73, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 95 | AMD_RIB = 0x76, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 96 | AMD_FW_AMF_SRAM = 0x85, |
| 97 | AMD_FW_AMF_DRAM = 0x86, |
| 98 | AMD_FW_AMF_WLAN = 0x88, |
| 99 | AMD_FW_AMF_MFD = 0x89, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 100 | AMD_FW_MPDMA_TF = 0x8c, |
Karthikeyan Ramasubramanian | 0ab04d2 | 2022-05-03 18:16:34 -0600 | [diff] [blame] | 101 | AMD_TA_IKEK = 0x8d, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 102 | AMD_FW_MPCCX = 0x90, |
Arthur Heymans | 1f05c80 | 2022-10-04 17:50:21 +0200 | [diff] [blame] | 103 | AMD_FW_GMI3_PHY = 0x91, |
| 104 | AMD_FW_MPDMA_PM = 0x92, |
Zheng Bao | 8eba662 | 2022-10-16 20:29:03 +0800 | [diff] [blame] | 105 | AMD_FW_LSDMA = 0x94, |
| 106 | AMD_FW_C20_MP = 0x95, |
| 107 | AMD_FW_FCFG_TABLE = 0x98, |
| 108 | AMD_FW_MINIMSMU = 0x9a, |
| 109 | AMD_FW_SRAM_FW_EXT = 0x9d, |
Fred Reitberger | c4f3a33 | 2023-02-07 12:12:40 -0500 | [diff] [blame] | 110 | AMD_FW_UMSMU = 0xa2, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 111 | AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ |
| 112 | AMD_FW_GEC, |
| 113 | AMD_FW_XHCI, |
| 114 | AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ |
| 115 | AMD_FW_SKIP /* This is for non-applicable options. */ |
| 116 | } amd_fw_type; |
| 117 | |
| 118 | typedef enum _amd_bios_type { |
Ritul Guru | 9a321f3 | 2022-07-29 11:06:40 +0530 | [diff] [blame] | 119 | AMD_BIOS_RTM_PUBKEY = 0x05, |
| 120 | AMD_BIOS_SIG = 0x07, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 121 | AMD_BIOS_APCB = 0x60, |
| 122 | AMD_BIOS_APOB = 0x61, |
| 123 | AMD_BIOS_BIN = 0x62, |
| 124 | AMD_BIOS_APOB_NV = 0x63, |
| 125 | AMD_BIOS_PMUI = 0x64, |
| 126 | AMD_BIOS_PMUD = 0x65, |
| 127 | AMD_BIOS_UCODE = 0x66, |
| 128 | AMD_BIOS_APCB_BK = 0x68, |
Arthur Heymans | 93aa090 | 2023-07-13 11:37:57 +0200 | [diff] [blame] | 129 | AMD_BIOS_EARLY_VGA = 0x69, |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 130 | AMD_BIOS_MP2_CFG = 0x6a, |
| 131 | AMD_BIOS_PSP_SHARED_MEM = 0x6b, |
| 132 | AMD_BIOS_L2_PTR = 0x70, |
| 133 | AMD_BIOS_INVALID, |
| 134 | AMD_BIOS_SKIP |
| 135 | } amd_bios_type; |
| 136 | |
Robert Zieba | 29bc79f | 2022-03-14 15:59:12 -0600 | [diff] [blame] | 137 | typedef enum _amd_addr_mode { |
| 138 | AMD_ADDR_PHYSICAL = 0, /* Physical address */ |
| 139 | AMD_ADDR_REL_BIOS, /* Relative to beginning of image */ |
| 140 | AMD_ADDR_REL_TAB, /* Relative to table */ |
| 141 | AMD_ADDR_REL_SLOT, /* Relative to slot */ |
| 142 | } amd_addr_mode; |
| 143 | |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 144 | struct second_gen_efs { /* todo: expand for Server products */ |
| 145 | int gen:1; /* Client products only use bit 0 */ |
| 146 | int reserved:31; |
| 147 | } __attribute__((packed)); |
| 148 | |
| 149 | #define EFS_SECOND_GEN 0 |
Zheng Bao | 487d045 | 2022-04-03 12:50:07 +0800 | [diff] [blame] | 150 | #define EFS_BEFORE_SECOND_GEN 1 |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 151 | |
| 152 | typedef struct _embedded_firmware { |
| 153 | uint32_t signature; /* 0x55aa55aa */ |
| 154 | uint32_t imc_entry; |
| 155 | uint32_t gec_entry; |
| 156 | uint32_t xhci_entry; |
Felix Held | ad68b07 | 2021-10-18 14:00:35 +0200 | [diff] [blame] | 157 | uint32_t psp_directory; |
Felix Held | c5c7fa4 | 2023-03-20 16:02:47 +0100 | [diff] [blame] | 158 | uint32_t new_psp_directory; /* also used as combo_psp_directory */ |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 159 | uint32_t bios0_entry; /* todo: add way to select correct entry */ |
| 160 | uint32_t bios1_entry; |
| 161 | uint32_t bios2_entry; |
| 162 | struct second_gen_efs efs_gen; |
| 163 | uint32_t bios3_entry; |
| 164 | uint32_t reserved_2Ch; |
| 165 | uint32_t promontory_fw_ptr; |
| 166 | uint32_t lp_promontory_fw_ptr; |
| 167 | uint32_t reserved_38h; |
| 168 | uint32_t reserved_3Ch; |
| 169 | uint8_t spi_readmode_f15_mod_60_6f; |
| 170 | uint8_t fast_speed_new_f15_mod_60_6f; |
| 171 | uint8_t reserved_42h; |
| 172 | uint8_t spi_readmode_f17_mod_00_2f; |
| 173 | uint8_t spi_fastspeed_f17_mod_00_2f; |
| 174 | uint8_t qpr_dummy_cycle_f17_mod_00_2f; |
| 175 | uint8_t reserved_46h; |
| 176 | uint8_t spi_readmode_f17_mod_30_3f; |
| 177 | uint8_t spi_fastspeed_f17_mod_30_3f; |
| 178 | uint8_t micron_detect_f17_mod_30_3f; |
| 179 | uint8_t reserved_4Ah; |
| 180 | uint8_t reserved_4Bh; |
| 181 | uint32_t reserved_4Ch; |
| 182 | } __attribute__((packed, aligned(16))) embedded_firmware; |
| 183 | |
| 184 | typedef struct _psp_directory_header { |
| 185 | uint32_t cookie; |
| 186 | uint32_t checksum; |
| 187 | uint32_t num_entries; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 188 | union { |
| 189 | uint32_t additional_info; |
| 190 | struct { |
| 191 | uint32_t dir_size:10; |
| 192 | uint32_t spi_block_size:4; |
| 193 | uint32_t base_addr:15; |
| 194 | uint32_t address_mode:2; |
| 195 | uint32_t not_used:1; |
| 196 | } __attribute__((packed)) additional_info_fields; |
| 197 | }; |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 198 | } __attribute__((packed, aligned(16))) psp_directory_header; |
| 199 | |
| 200 | typedef struct _psp_directory_entry { |
| 201 | uint8_t type; |
| 202 | uint8_t subprog; |
Zheng Bao | 5ca1343 | 2022-10-16 20:18:40 +0800 | [diff] [blame] | 203 | union { |
| 204 | uint16_t rsvd; |
| 205 | struct { |
| 206 | uint8_t rom_id:2; |
| 207 | uint8_t writable:1; |
| 208 | uint8_t inst:4; |
| 209 | uint8_t rsvd_1:1; |
| 210 | uint8_t rsvd_2:8; |
| 211 | } __attribute__((packed)); |
| 212 | }; |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 213 | uint32_t size; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 214 | uint64_t addr:62; /* or a value in some cases */ |
| 215 | uint64_t address_mode:2; |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 216 | } __attribute__((packed)) psp_directory_entry; |
| 217 | |
| 218 | typedef struct _psp_directory_table { |
| 219 | psp_directory_header header; |
| 220 | psp_directory_entry entries[]; |
| 221 | } __attribute__((packed, aligned(16))) psp_directory_table; |
| 222 | |
Fred Reitberger | a194e62 | 2023-03-09 12:33:52 -0500 | [diff] [blame] | 223 | #define MAX_PSP_ENTRIES 0xff |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 224 | |
| 225 | typedef struct _psp_combo_header { |
| 226 | uint32_t cookie; |
| 227 | uint32_t checksum; |
| 228 | uint32_t num_entries; |
| 229 | uint32_t lookup; |
| 230 | uint64_t reserved[2]; |
| 231 | } __attribute__((packed, aligned(16))) psp_combo_header; |
| 232 | |
| 233 | typedef struct _psp_combo_entry { |
| 234 | uint32_t id_sel; |
| 235 | uint32_t id; |
| 236 | uint64_t lvl2_addr; |
| 237 | } __attribute__((packed)) psp_combo_entry; |
| 238 | |
| 239 | typedef struct _psp_combo_directory { |
| 240 | psp_combo_header header; |
| 241 | psp_combo_entry entries[]; |
| 242 | } __attribute__((packed, aligned(16))) psp_combo_directory; |
| 243 | |
Zheng Bao | 0e3d18b | 2023-03-07 15:28:57 +0800 | [diff] [blame] | 244 | #define MAX_COMBO_ENTRIES 2 |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 245 | |
| 246 | typedef struct _bios_directory_hdr { |
| 247 | uint32_t cookie; |
| 248 | uint32_t checksum; |
| 249 | uint32_t num_entries; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 250 | union { |
| 251 | uint32_t additional_info; |
| 252 | struct { |
| 253 | uint32_t dir_size:10; |
| 254 | uint32_t spi_block_size:4; |
| 255 | uint32_t base_addr:15; |
| 256 | uint32_t address_mode:2; |
| 257 | uint32_t not_used:1; |
| 258 | } __attribute__((packed)) additional_info_fields; |
| 259 | }; |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 260 | } __attribute__((packed, aligned(16))) bios_directory_hdr; |
| 261 | |
| 262 | typedef struct _bios_directory_entry { |
| 263 | uint8_t type; |
| 264 | uint8_t region_type; |
| 265 | int reset:1; |
| 266 | int copy:1; |
| 267 | int ro:1; |
| 268 | int compressed:1; |
| 269 | int inst:4; |
| 270 | uint8_t subprog; /* b[7:3] reserved */ |
| 271 | uint32_t size; |
Zheng Bao | 6fff249 | 2021-11-15 19:53:21 +0800 | [diff] [blame] | 272 | uint64_t source:62; |
| 273 | uint64_t address_mode:2; |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 274 | uint64_t dest; |
| 275 | } __attribute__((packed)) bios_directory_entry; |
| 276 | |
| 277 | typedef struct _bios_directory_table { |
| 278 | bios_directory_hdr header; |
| 279 | bios_directory_entry entries[]; |
| 280 | } bios_directory_table; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 281 | |
Altamshali Hirani | 8915abe | 2022-03-17 13:26:31 -0500 | [diff] [blame] | 282 | #define MAX_BIOS_ENTRIES 0x2f |
| 283 | |
Zheng Bao | 3335133 | 2021-10-30 16:53:23 +0800 | [diff] [blame] | 284 | #define BDT_LVL1 (1 << 0) |
| 285 | #define BDT_LVL2 (1 << 1) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 286 | #define BDT_LVL1_AB (1 << 2) |
| 287 | #define BDT_LVL2_AB (1 << 3) |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 288 | #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 289 | #define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB) |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 290 | typedef struct _amd_bios_entry { |
| 291 | amd_bios_type type; |
| 292 | char *filename; |
| 293 | int subpr; |
| 294 | int region_type; |
| 295 | int reset; |
| 296 | int copy; |
| 297 | int ro; |
| 298 | int zlib; |
| 299 | int inst; |
| 300 | uint64_t src; |
| 301 | uint64_t dest; |
| 302 | size_t size; |
| 303 | int level; |
| 304 | } amd_bios_entry; |
| 305 | |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 306 | typedef struct _ish_directory_table { |
| 307 | uint32_t checksum; |
| 308 | uint32_t boot_priority; |
| 309 | uint32_t update_retry_count; |
| 310 | uint8_t glitch_retry_count; |
| 311 | uint8_t glitch_higherbits_reserved[3]; |
| 312 | uint32_t pl2_location; |
| 313 | uint32_t psp_id; |
| 314 | uint32_t slot_max_size; |
| 315 | uint32_t reserved; |
| 316 | } __attribute__((packed)) ish_directory_table; |
| 317 | |
Zheng Bao | 6be1ab6 | 2021-05-26 10:16:33 +0800 | [diff] [blame] | 318 | #define EMBEDDED_FW_SIGNATURE 0x55aa55aa |
| 319 | #define PSP_COOKIE 0x50535024 /* 'PSP$' */ |
| 320 | #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ |
| 321 | #define PSP2_COOKIE 0x50535032 /* 'PSP2' */ |
Zheng Bao | 96a3371 | 2021-06-11 15:54:40 +0800 | [diff] [blame] | 322 | #define BHD_COOKIE 0x44484224 /* 'DHB$ */ |
| 323 | #define BHDL2_COOKIE 0x324c4224 /* '2LB$ */ |
Zheng Bao | 84fb9ea | 2022-08-18 15:54:47 +0800 | [diff] [blame] | 324 | #define BHD2_COOKIE 0x44484232 /* 'DHB2' */ |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 325 | |
Zheng Bao | 3335133 | 2021-10-30 16:53:23 +0800 | [diff] [blame] | 326 | #define PSP_LVL1 (1 << 0) |
| 327 | #define PSP_LVL2 (1 << 1) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 328 | #define PSP_LVL1_AB (1 << 2) |
| 329 | #define PSP_LVL2_AB (1 << 3) |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 330 | #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 331 | #define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 332 | |
| 333 | typedef struct _amd_fw_entry_hash { |
| 334 | uint16_t fw_id; |
| 335 | uint16_t subtype; |
| 336 | uint32_t sha_len; |
| 337 | uint8_t sha[SHA384_DIGEST_LENGTH]; |
| 338 | } amd_fw_entry_hash; |
| 339 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 340 | typedef struct _amd_fw_entry { |
| 341 | amd_fw_type type; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 342 | /* Mendocino and later SoCs use fw_id instead of fw_type. fw_type is still around |
| 343 | for backwards compatibility. fw_id can be populated from the PSP binary file. */ |
| 344 | uint16_t fw_id; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 345 | char *filename; |
| 346 | uint8_t subprog; |
Zheng Bao | 5ca1343 | 2022-10-16 20:18:40 +0800 | [diff] [blame] | 347 | uint8_t inst; |
Ritul Guru | a2cb340 | 2022-08-29 00:51:08 +0530 | [diff] [blame] | 348 | uint64_t dest; |
| 349 | size_t size; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 350 | int level; |
| 351 | uint64_t other; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 352 | /* If the binary is signed and the tool is invoked to keep the signed binaries separate, |
| 353 | then this field is populated with the offset of the concerned PSP binary (relative to |
| 354 | BIOS or PSP Directory table). */ |
| 355 | uint64_t addr_signed; |
| 356 | uint32_t file_size; |
| 357 | /* Some files that don't have amd_fw_header have to be skipped from hashing. These files |
| 358 | include but not limited to: *iKek*, *.tkn, *.stkn */ |
| 359 | bool skip_hashing; |
Karthikeyan Ramasubramanian | d7a5d9e | 2023-05-03 13:34:41 -0600 | [diff] [blame] | 360 | uint8_t hash_tbl_id; |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 361 | uint32_t num_hash_entries; |
| 362 | amd_fw_entry_hash *hash_entries; |
Grzegorz Bernacki | dfdf81c | 2023-04-05 09:35:42 +0000 | [diff] [blame] | 363 | bool generate_manifest; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 364 | } amd_fw_entry; |
| 365 | |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 366 | /* Most PSP binaries, if not all, have the following header format. */ |
| 367 | struct amd_fw_header { |
| 368 | uint8_t reserved_0[20]; |
| 369 | uint32_t fw_size_signed; |
| 370 | uint8_t reserved_18[24]; |
| 371 | /* 1 if the image is signed, 0 otherwise */ |
| 372 | uint32_t sig_opt; |
| 373 | uint32_t sig_id; |
| 374 | uint8_t sig_param[16]; |
| 375 | uint32_t comp_opt; |
| 376 | uint8_t reserved_4c[4]; |
| 377 | uint32_t uncomp_size; |
| 378 | uint32_t comp_size; |
| 379 | /* Starting MDN fw_id is populated instead of fw_type. */ |
| 380 | uint16_t fw_id; |
Grzegorz Bernacki | dfdf81c | 2023-04-05 09:35:42 +0000 | [diff] [blame] | 381 | uint8_t reserved_5a[6]; |
| 382 | uint8_t version[4]; |
| 383 | uint8_t reserved_64[8]; |
Kangheui Won | 3c164e1 | 2021-12-03 20:25:05 +1100 | [diff] [blame] | 384 | uint32_t size_total; |
| 385 | uint8_t reserved_70[12]; |
| 386 | /* Starting MDN fw_id is populated instead of fw_type. fw_type will still be around |
| 387 | for backwards compatibility. */ |
| 388 | uint8_t fw_type; |
| 389 | uint8_t fw_subtype; |
| 390 | uint8_t fw_subprog; |
| 391 | uint8_t reserved_7f; |
| 392 | uint8_t reserved_80[128]; |
| 393 | } __packed; |
| 394 | |
Karthikeyan Ramasubramanian | d7a5d9e | 2023-05-03 13:34:41 -0600 | [diff] [blame] | 395 | /* Based on the available PSP resources and increasing number of signed PSP binaries, |
| 396 | AMD recommends to split the hash table into 3 parts for now. */ |
| 397 | #define MAX_NUM_HASH_TABLES 3 |
Kangheui Won | 5b84dfd | 2021-12-21 15:45:06 +1100 | [diff] [blame] | 398 | struct psp_fw_hash_table { |
| 399 | uint16_t version; |
| 400 | uint16_t no_of_entries_256; |
| 401 | uint16_t no_of_entries_384; |
| 402 | /* The next 2 elements are pointers to arrays of SHA256 and SHA384 entries. */ |
| 403 | /* It does not make sense to store pointers in the CBFS file */ |
| 404 | } __packed; |
| 405 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 406 | typedef struct _amd_cb_config { |
Zheng Bao | ba3af5e | 2021-11-04 18:56:47 +0800 | [diff] [blame] | 407 | bool have_whitelist; |
| 408 | bool unlock_secure; |
| 409 | bool use_secureos; |
| 410 | bool load_mp2_fw; |
| 411 | bool multi_level; |
| 412 | bool s0i3; |
Zheng Bao | c3007f3 | 2022-04-03 12:53:51 +0800 | [diff] [blame] | 413 | bool second_gen; |
Zheng Bao | 6c5ec8e | 2022-02-11 11:51:26 +0800 | [diff] [blame] | 414 | bool have_mb_spl; |
Zheng Bao | 990d154 | 2021-09-17 13:24:54 +0800 | [diff] [blame] | 415 | bool recovery_ab; |
Karthikeyan Ramasubramanian | ad06bae | 2022-04-08 14:19:55 -0600 | [diff] [blame] | 416 | bool recovery_ab_single_copy; |
Zheng Bao | fdd47ef | 2021-09-17 13:30:08 +0800 | [diff] [blame] | 417 | bool need_ish; |
Zheng Bao | 993b43f | 2021-11-10 12:21:46 +0800 | [diff] [blame] | 418 | bool use_combo; |
Karthikeyan Ramasubramanian | 8d88561 | 2023-03-09 17:39:31 -0700 | [diff] [blame] | 419 | bool have_apcb_bk; |
Zheng Bao | 4bf6f49 | 2023-01-25 22:37:29 +0800 | [diff] [blame] | 420 | enum platform soc_id; |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 421 | } amd_cb_config; |
| 422 | |
| 423 | void register_fw_fuse(char *str); |
Zheng Bao | 994ff52 | 2023-03-09 11:43:55 +0800 | [diff] [blame] | 424 | uint8_t process_config(FILE *config, amd_cb_config *cb_config); |
Zheng Bao | f080cd5 | 2023-03-22 12:50:36 +0800 | [diff] [blame] | 425 | void process_signed_psp_firmwares(const char *signed_rom, |
| 426 | amd_fw_entry *fw_table, |
| 427 | uint64_t signed_start_addr, |
| 428 | enum platform soc_id); |
| 429 | void write_or_fail(int fd, void *ptr, size_t size); |
| 430 | ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size); |
| 431 | ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size); |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 432 | #define OK 0 |
| 433 | |
| 434 | #define LINE_EOF (1) |
| 435 | #define LINE_TOO_LONG (2) |
| 436 | |
Zheng Bao | c5e28ab | 2020-10-28 11:38:09 +0800 | [diff] [blame] | 437 | #endif /* _AMD_FW_TOOL_H_ */ |