Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/mmio.h> |
| 5 | #include <bootstate.h> |
Raul E Rangel | be2b5ac | 2020-06-04 16:36:33 -0600 | [diff] [blame] | 6 | #include <cpu/amd/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 7 | #include <cpu/x86/smm.h> |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 8 | #include <cpu/x86/msr.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
| 12 | #include <cbmem.h> |
Kyösti Mälkki | 5daa1d3 | 2020-06-14 12:01:58 +0300 | [diff] [blame] | 13 | #include <acpi/acpi_gnvs.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 14 | #include <amdblocks/amd_pci_util.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 15 | #include <amdblocks/reset.h> |
| 16 | #include <amdblocks/acpimmio.h> |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 17 | #include <amdblocks/espi.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 18 | #include <amdblocks/lpc.h> |
| 19 | #include <amdblocks/acpi.h> |
Felix Held | 875e5aa | 2020-12-01 00:34:11 +0100 | [diff] [blame] | 20 | #include <amdblocks/smbus.h> |
Furquan Shaikh | 13b8158 | 2020-05-09 17:24:42 -0700 | [diff] [blame] | 21 | #include <amdblocks/spi.h> |
Aaron Durbin | aa8f165 | 2020-08-17 17:41:28 -0600 | [diff] [blame] | 22 | #include <soc/acpi.h> |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 23 | #include <soc/cpu.h> |
Felix Held | 5b01f2b | 2020-05-20 16:01:43 +0200 | [diff] [blame] | 24 | #include <soc/i2c.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | #include <soc/southbridge.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 26 | #include <soc/smi.h> |
Felix Held | 9412b3e | 2020-06-18 15:54:43 +0200 | [diff] [blame] | 27 | #include <soc/uart.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | #include <soc/amd_pci_int_defs.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 29 | #include <soc/pci_devs.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 30 | #include <soc/nvs.h> |
| 31 | #include <types.h> |
Furquan Shaikh | 69c2811 | 2020-04-28 18:57:52 -0700 | [diff] [blame] | 32 | #include "chip.h" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 33 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 34 | /* |
| 35 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
| 36 | * provides a visible association with the index, therefore helping |
| 37 | * maintainability of table. If a new index/name is defined in |
| 38 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 39 | * Order is not important. |
| 40 | */ |
| 41 | const static struct irq_idx_name irq_association[] = { |
| 42 | { PIRQ_A, "INTA#" }, |
| 43 | { PIRQ_B, "INTB#" }, |
| 44 | { PIRQ_C, "INTC#" }, |
| 45 | { PIRQ_D, "INTD#" }, |
| 46 | { PIRQ_E, "INTE#" }, |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 47 | { PIRQ_F, "INTF#/GENINT2" }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 48 | { PIRQ_G, "INTG#" }, |
| 49 | { PIRQ_H, "INTH#" }, |
| 50 | { PIRQ_MISC, "Misc" }, |
| 51 | { PIRQ_MISC0, "Misc0" }, |
| 52 | { PIRQ_MISC1, "Misc1" }, |
| 53 | { PIRQ_MISC2, "Misc2" }, |
| 54 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 55 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 56 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 57 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
| 58 | { PIRQ_SCI, "SCI" }, |
| 59 | { PIRQ_SMBUS, "SMBUS" }, |
| 60 | { PIRQ_ASF, "ASF" }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 61 | { PIRQ_PMON, "PerMon" }, |
| 62 | { PIRQ_SD, "SD" }, |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 63 | { PIRQ_SDIO, "SDIO" }, |
| 64 | { PIRQ_CIR, "CIR" }, |
| 65 | { PIRQ_GPIOA, "GPIOa" }, |
| 66 | { PIRQ_GPIOB, "GPIOb" }, |
| 67 | { PIRQ_GPIOC, "GPIOc" }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 68 | { PIRQ_SATA, "SATA" }, |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 69 | { PIRQ_EMMC, "eMMC" }, |
| 70 | { PIRQ_GPP0, "GPP0" }, |
| 71 | { PIRQ_GPP1, "GPP1" }, |
| 72 | { PIRQ_GPP2, "GPP2" }, |
| 73 | { PIRQ_GPP3, "GPP3" }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 74 | { PIRQ_GPIO, "GPIO" }, |
| 75 | { PIRQ_I2C0, "I2C0" }, |
| 76 | { PIRQ_I2C1, "I2C1" }, |
| 77 | { PIRQ_I2C2, "I2C2" }, |
| 78 | { PIRQ_I2C3, "I2C3" }, |
| 79 | { PIRQ_UART0, "UART0" }, |
| 80 | { PIRQ_UART1, "UART1" }, |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 81 | { PIRQ_I2C4, "I2C4" }, |
| 82 | { PIRQ_I2C5, "I2C5" }, |
| 83 | { PIRQ_UART2, "UART2" }, |
| 84 | { PIRQ_UART3, "UART3" }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 88 | { |
| 89 | *size = ARRAY_SIZE(irq_association); |
| 90 | return irq_association; |
| 91 | } |
| 92 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 93 | static void sb_enable_cf9_io(void) |
| 94 | { |
| 95 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 96 | |
| 97 | pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); |
| 98 | } |
| 99 | |
| 100 | static void sb_enable_legacy_io(void) |
| 101 | { |
| 102 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 103 | |
| 104 | pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); |
| 105 | } |
| 106 | |
Marshall Dawson | 0bd0806 | 2019-06-20 11:03:06 -0600 | [diff] [blame] | 107 | void sb_clk_output_48Mhz(void) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 108 | { |
| 109 | u32 ctrl; |
| 110 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 111 | ctrl = misc_read32(MISC_CLK_CNTL1); |
Marshall Dawson | 0bd0806 | 2019-06-20 11:03:06 -0600 | [diff] [blame] | 112 | ctrl |= BP_X48M0_OUTPUT_EN; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 113 | misc_write32(MISC_CLK_CNTL1, ctrl); |
| 114 | } |
| 115 | |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 116 | static void lpc_configure_decodes(void) |
| 117 | { |
| 118 | if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80)) |
| 119 | lpc_enable_port80(); |
| 120 | } |
| 121 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 122 | /* Before console init */ |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 123 | void fch_pre_init(void) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 124 | { |
Furquan Shaikh | ed8ceab | 2020-05-09 17:35:02 -0700 | [diff] [blame] | 125 | lpc_early_init(); |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 126 | |
| 127 | if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) |
| 128 | lpc_configure_decodes(); |
| 129 | |
Furquan Shaikh | 13b8158 | 2020-05-09 17:24:42 -0700 | [diff] [blame] | 130 | fch_spi_early_init(); |
Michał Żygowski | 73a544d | 2019-11-24 14:16:34 +0100 | [diff] [blame] | 131 | enable_acpimmio_decode_pm04(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 132 | fch_smbus_init(); |
| 133 | sb_enable_cf9_io(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 134 | sb_enable_legacy_io(); |
| 135 | enable_aoac_devices(); |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 136 | sb_reset_i2c_slaves(); |
Raul E Rangel | 4f5936b | 2020-06-11 16:27:49 -0600 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * On reset Range_0 defaults to enabled. We want to start with a clean |
| 140 | * slate to not have things unexpectedly enabled. |
| 141 | */ |
| 142 | clear_uart_legacy_config(); |
| 143 | |
Felix Held | 097e449 | 2020-06-16 15:35:20 +0200 | [diff] [blame] | 144 | if (CONFIG(PICASSO_CONSOLE_UART)) |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 145 | set_uart_config(CONFIG_UART_FOR_CONSOLE); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 149 | const char *const bit_names[]) |
| 150 | { |
| 151 | int i; |
| 152 | |
| 153 | if (!status) |
| 154 | return; |
| 155 | |
| 156 | for (i = num_bits - 1; i >= 0; i--) { |
| 157 | if (status & (1 << i)) { |
| 158 | if (bit_names[i]) |
| 159 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 160 | else |
| 161 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 162 | } |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | static void sb_print_pmxc0_status(void) |
| 167 | { |
| 168 | /* PMxC0 S5/Reset Status shows the source of previous reset. */ |
| 169 | uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); |
| 170 | |
| 171 | static const char *const pmxc0_status_bits[32] = { |
| 172 | [0] = "ThermalTrip", |
| 173 | [1] = "FourSecondPwrBtn", |
| 174 | [2] = "Shutdown", |
| 175 | [3] = "ThermalTripFromTemp", |
| 176 | [4] = "RemotePowerDownFromASF", |
| 177 | [5] = "ShutDownFan0", |
| 178 | [16] = "UserRst", |
| 179 | [17] = "SoftPciRst", |
| 180 | [18] = "DoInit", |
| 181 | [19] = "DoReset", |
| 182 | [20] = "DoFullReset", |
| 183 | [21] = "SleepReset", |
| 184 | [22] = "KbReset", |
| 185 | [23] = "LtReset", |
| 186 | [24] = "FailBootRst", |
| 187 | [25] = "WatchdogIssueReset", |
| 188 | [26] = "RemoteResetFromASF", |
| 189 | [27] = "SyncFlood", |
| 190 | [28] = "HangReset", |
| 191 | [29] = "EcWatchdogRst", |
| 192 | }; |
| 193 | |
| 194 | printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); |
| 195 | print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, |
| 196 | pmxc0_status_bits); |
| 197 | printk(BIOS_DEBUG, "\n"); |
| 198 | } |
| 199 | |
| 200 | /* After console init */ |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 201 | void fch_early_init(void) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 202 | { |
| 203 | sb_print_pmxc0_status(); |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 204 | i2c_soc_early_init(); |
Aaron Durbin | 1d0b99b | 2020-04-11 11:58:57 -0600 | [diff] [blame] | 205 | |
| 206 | if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) |
| 207 | lpc_disable_spi_rom_sharing(); |
Furquan Shaikh | 702cf30 | 2020-05-09 18:30:51 -0700 | [diff] [blame] | 208 | |
| 209 | if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { |
| 210 | espi_setup(); |
| 211 | espi_configure_decodes(); |
| 212 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | void sb_enable(struct device *dev) |
| 216 | { |
| 217 | printk(BIOS_DEBUG, "%s\n", __func__); |
| 218 | } |
| 219 | |
| 220 | static void sb_init_acpi_ports(void) |
| 221 | { |
| 222 | u32 reg; |
| 223 | |
| 224 | /* We use some of these ports in SMM regardless of whether or not |
| 225 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 226 | */ |
| 227 | |
| 228 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 229 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 230 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 231 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 232 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 233 | if (CONFIG(HAVE_SMI_HANDLER)) { |
| 234 | /* APMC - SMI Command Port */ |
| 235 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
| 236 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
| 237 | |
| 238 | /* SMI on SlpTyp requires sending SMI before completion |
| 239 | * response of the I/O write. The BKDG also specifies |
| 240 | * clearing ForceStpClkRetry for SMI trapping. |
| 241 | */ |
| 242 | reg = pm_read32(PM_PCI_CTRL); |
| 243 | reg |= FORCE_SLPSTATE_RETRY; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 244 | pm_write32(PM_PCI_CTRL, reg); |
| 245 | |
| 246 | /* Disable SlpTyp feature */ |
| 247 | reg = pm_read8(PM_RST_CTRL1); |
| 248 | reg &= ~SLPTYPE_CONTROL_EN; |
| 249 | pm_write8(PM_RST_CTRL1, reg); |
| 250 | |
| 251 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
| 252 | } else { |
| 253 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 254 | } |
| 255 | |
| 256 | /* Decode ACPI registers and enable standard features */ |
| 257 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 258 | PM_ACPI_GLOBAL_EN | |
| 259 | PM_ACPI_RTC_EN_EN | |
| 260 | PM_ACPI_TIMER_EN_EN); |
| 261 | } |
| 262 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 263 | static void set_nvs_sws(void *unused) |
| 264 | { |
Aaron Durbin | aa8f165 | 2020-08-17 17:41:28 -0600 | [diff] [blame] | 265 | struct chipset_state *state; |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 266 | struct global_nvs *gnvs; |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 267 | |
Aaron Durbin | 404a5c3 | 2020-08-14 16:27:27 -0600 | [diff] [blame] | 268 | state = cbmem_find(CBMEM_ID_POWER_STATE); |
| 269 | if (state == NULL) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 270 | return; |
Kyösti Mälkki | 5daa1d3 | 2020-06-14 12:01:58 +0300 | [diff] [blame] | 271 | gnvs = acpi_get_gnvs(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 272 | if (gnvs == NULL) |
| 273 | return; |
| 274 | |
Aaron Durbin | aa8f165 | 2020-08-17 17:41:28 -0600 | [diff] [blame] | 275 | acpi_fill_gnvs(gnvs, &state->gpe_state); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); |
| 279 | |
Matt Papageorge | ab83b43 | 2020-06-26 08:47:00 -0500 | [diff] [blame] | 280 | /* |
| 281 | * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks |
| 282 | * and unneeded for Raven/Picasso so gate them to save power. |
| 283 | */ |
| 284 | static void al2ahb_clock_gate(void) |
| 285 | { |
| 286 | uint8_t al2ahb_val; |
| 287 | uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; |
| 288 | |
| 289 | al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); |
| 290 | al2ahb_val |= AL2AHB_CLK_GATE_EN; |
| 291 | write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); |
| 292 | al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); |
| 293 | al2ahb_val |= AL2AHB_HCLK_GATE_EN; |
| 294 | write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); |
| 295 | } |
| 296 | |
Felix Held | 82a0a63 | 2020-08-28 01:40:20 +0200 | [diff] [blame] | 297 | /* configure the genral purpose PCIe clock outputs according to the devicetree settings */ |
| 298 | static void gpp_clk_setup(void) |
| 299 | { |
| 300 | const struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 301 | |
| 302 | /* look-up table to be able to iterate over the PCIe clock output settings */ |
| 303 | const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { |
| 304 | GPP_CLK0_REQ_SHIFT, |
| 305 | GPP_CLK1_REQ_SHIFT, |
| 306 | GPP_CLK2_REQ_SHIFT, |
| 307 | GPP_CLK3_REQ_SHIFT, |
| 308 | GPP_CLK4_REQ_SHIFT, |
| 309 | GPP_CLK5_REQ_SHIFT, |
| 310 | GPP_CLK6_REQ_SHIFT, |
| 311 | }; |
| 312 | |
| 313 | uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); |
| 314 | |
| 315 | for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { |
| 316 | gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); |
| 317 | /* |
| 318 | * The remapping of values is done so that the default of the enum used for the |
| 319 | * devicetree settings is the clock being enabled, so that a missing devicetree |
| 320 | * configuration for this will result in an always active clock and not an |
| 321 | * inactive PCIe clock output. |
| 322 | */ |
| 323 | switch (cfg->gpp_clk_config[i]) { |
| 324 | case GPP_CLK_REQ: |
| 325 | gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); |
| 326 | break; |
| 327 | case GPP_CLK_OFF: |
| 328 | gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); |
| 329 | break; |
| 330 | case GPP_CLK_ON: |
| 331 | default: |
| 332 | gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); |
| 337 | } |
| 338 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 339 | void southbridge_init(void *chip_info) |
| 340 | { |
Aaron Durbin | aa8f165 | 2020-08-17 17:41:28 -0600 | [diff] [blame] | 341 | struct chipset_state *state; |
Aaron Durbin | 404a5c3 | 2020-08-14 16:27:27 -0600 | [diff] [blame] | 342 | |
Aaron Durbin | 09f60ff | 2020-04-09 15:24:50 -0600 | [diff] [blame] | 343 | i2c_soc_init(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 344 | sb_init_acpi_ports(); |
Aaron Durbin | 404a5c3 | 2020-08-14 16:27:27 -0600 | [diff] [blame] | 345 | |
Aaron Durbin | c30981c | 2020-08-14 16:54:44 -0600 | [diff] [blame] | 346 | state = cbmem_find(CBMEM_ID_POWER_STATE); |
Aaron Durbin | aa8f165 | 2020-08-17 17:41:28 -0600 | [diff] [blame] | 347 | if (state) { |
| 348 | acpi_pm_gpe_add_events_print_events(&state->gpe_state); |
| 349 | gpio_add_events(&state->gpio_state); |
| 350 | } |
Aaron Durbin | 404a5c3 | 2020-08-14 16:27:27 -0600 | [diff] [blame] | 351 | acpi_clear_pm_gpe_status(); |
| 352 | |
Matt Papageorge | ab83b43 | 2020-06-26 08:47:00 -0500 | [diff] [blame] | 353 | al2ahb_clock_gate(); |
Felix Held | 82a0a63 | 2020-08-28 01:40:20 +0200 | [diff] [blame] | 354 | |
| 355 | gpp_clk_setup(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 356 | } |
| 357 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 358 | void southbridge_final(void *chip_info) |
| 359 | { |
| 360 | uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; |
| 361 | |
| 362 | if (CONFIG(MAINBOARD_POWER_RESTORE)) |
| 363 | restored_power = PM_RESTORE_S0_IF_PREV_S0; |
| 364 | pm_write8(PM_RTC_SHADOW, restored_power); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | /* |
| 368 | * Update the PCI devices with a valid IRQ number |
| 369 | * that is set in the mainboard PCI_IRQ structures. |
| 370 | */ |
| 371 | static void set_pci_irqs(void *unused) |
| 372 | { |
| 373 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 374 | write_pci_int_table(); |
| 375 | |
| 376 | /* Write IRQs for all devicetree enabled devices */ |
| 377 | write_pci_cfg_irqs(); |
| 378 | } |
| 379 | |
| 380 | /* |
| 381 | * Hook this function into the PCI state machine |
| 382 | * on entry into BS_DEV_ENABLE. |
| 383 | */ |
| 384 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |