Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
Raul E Rangel | 58a8ad1 | 2021-02-18 16:36:08 -0700 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Felix Held | 95f1bb8 | 2021-05-07 18:46:36 +0200 | [diff] [blame] | 5 | #include <amdblocks/alib.h> |
Arthur Heymans | ce17972 | 2023-06-07 15:27:18 +0200 | [diff] [blame] | 6 | #include <amdblocks/data_fabric.h> |
Raul E Rangel | 899be1b | 2021-02-05 15:50:20 -0700 | [diff] [blame] | 7 | #include <amdblocks/memmap.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 8 | #include <amdblocks/ioapic.h> |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 9 | #include <amdblocks/iomap.h> |
Felix Held | 43662b5 | 2023-07-18 20:36:34 +0200 | [diff] [blame^] | 10 | #include <amdblocks/root_complex.h> |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 11 | #include <arch/ioapic.h> |
Felix Held | a4ced63 | 2023-06-05 21:22:15 +0200 | [diff] [blame] | 12 | #include <arch/vga.h> |
John Zhao | f6f1f73 | 2020-06-26 10:00:02 -0700 | [diff] [blame] | 13 | #include <assert.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 14 | #include <cbmem.h> |
| 15 | #include <console/console.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 18 | #include <fsp/util.h> |
| 19 | #include <stdint.h> |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 20 | #include <soc/iomap.h> |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 21 | #include "chip.h" |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 22 | |
Felix Held | ef51157 | 2021-05-07 19:02:45 +0200 | [diff] [blame] | 23 | #define DPTC_TOTAL_UPDATE_PARAMS 4 |
| 24 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 25 | struct dptc_input { |
| 26 | uint16_t size; |
Felix Held | f061017 | 2021-05-07 19:21:08 +0200 | [diff] [blame] | 27 | struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 28 | } __packed; |
| 29 | |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 30 | #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ |
Felix Held | 3acafa2 | 2021-05-07 19:17:51 +0200 | [diff] [blame] | 31 | { \ |
| 32 | .size = sizeof(struct dptc_input), \ |
| 33 | .params = { \ |
| 34 | { \ |
| 35 | .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ |
| 36 | .value = _thermctllmit, \ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 37 | }, \ |
Felix Held | 3acafa2 | 2021-05-07 19:17:51 +0200 | [diff] [blame] | 38 | { \ |
| 39 | .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ |
| 40 | .value = _sustained, \ |
| 41 | }, \ |
| 42 | { \ |
| 43 | .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ |
| 44 | .value = _fast, \ |
| 45 | }, \ |
| 46 | { \ |
| 47 | .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ |
| 48 | .value = _slow, \ |
| 49 | }, \ |
| 50 | }, \ |
| 51 | } |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 52 | /* |
| 53 | * |
| 54 | * +--------------------------------+ |
| 55 | * | | |
| 56 | * | | |
| 57 | * | | |
| 58 | * | | |
| 59 | * | | |
| 60 | * | | |
| 61 | * | | |
| 62 | * reserved_dram_end +--------------------------------+ |
| 63 | * | | |
| 64 | * | verstage (if reqd) | |
| 65 | * | (VERSTAGE_SIZE) | |
| 66 | * +--------------------------------+ VERSTAGE_ADDR |
| 67 | * | | |
| 68 | * | FSP-M | |
| 69 | * | (FSP_M_SIZE) | |
| 70 | * +--------------------------------+ FSP_M_ADDR |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 71 | * | romstage | |
| 72 | * | (ROMSTAGE_SIZE) | |
Kyösti Mälkki | b3621f8 | 2020-12-04 19:51:17 +0200 | [diff] [blame] | 73 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 74 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 75 | * | bootblock | |
| 76 | * | (C_ENV_BOOTBLOCK_SIZE) | |
Kyösti Mälkki | b3621f8 | 2020-12-04 19:51:17 +0200 | [diff] [blame] | 77 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 78 | * | Unused hole | |
| 79 | * | (86KiB) | |
| 80 | * +--------------------------------+ |
| 81 | * | FMAP cache (FMAP_SIZE) | |
| 82 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 83 | * | Early Timestamp region (512B) | |
| 84 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 85 | * | Preram CBMEM console | |
| 86 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 87 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 88 | * | PSP shared (vboot workbuf) | |
| 89 | * | (PSP_SHAREDMEM_SIZE) | |
| 90 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 91 | * | APOB (64KiB) | |
| 92 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 93 | * | Early BSP stack | |
| 94 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 95 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 96 | * | DRAM | |
| 97 | * +--------------------------------+ 0x100000 |
| 98 | * | Option ROM | |
| 99 | * +--------------------------------+ 0xc0000 |
| 100 | * | Legacy VGA | |
| 101 | * +--------------------------------+ 0xa0000 |
| 102 | * | DRAM | |
| 103 | * +--------------------------------+ 0x0 |
| 104 | */ |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 105 | static void read_resources(struct device *dev) |
| 106 | { |
| 107 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
| 108 | unsigned int idx = 0; |
Felix Held | 2e81436 | 2022-11-10 22:44:18 +0100 | [diff] [blame] | 109 | const struct hob_header *hob_iterator; |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 110 | const struct hob_resource *res; |
| 111 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 112 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 113 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 114 | |
| 115 | early_reserved_dram_start = e->base; |
| 116 | early_reserved_dram_end = e->base + e->size; |
| 117 | |
Felix Held | af17f0b | 2022-03-02 23:36:55 +0100 | [diff] [blame] | 118 | /* The root complex has no PCI BARs implemented, so there's no need to call |
| 119 | pci_dev_read_resources for it */ |
| 120 | |
Felix Held | d0959dc | 2023-05-10 15:07:47 +0200 | [diff] [blame] | 121 | fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); |
| 122 | |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 123 | /* 0x0 - 0x9ffff */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 124 | ram_range(dev, idx++, 0, 0xa0000); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 125 | |
| 126 | /* 0xa0000 - 0xbffff: legacy VGA */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 127 | mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 128 | |
| 129 | /* 0xc0000 - 0xfffff: Option ROM */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 130 | reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 131 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 132 | /* 1MB - bottom of DRAM reserved for early coreboot usage */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 133 | ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 134 | |
| 135 | /* DRAM reserved for early coreboot usage */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 136 | reserved_ram_from_to(dev, idx++, early_reserved_dram_start, early_reserved_dram_end); |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 137 | |
| 138 | /* top of DRAM consumed early - low top usable RAM |
| 139 | * cbmem_top() accounts for low UMA and TSEG if they are used. */ |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 140 | ram_from_to(dev, idx++, early_reserved_dram_end, mem_usable); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 141 | |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 142 | mmconf_resource(dev, idx++); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 143 | |
Felix Held | dafc619 | 2022-11-10 18:19:36 +0100 | [diff] [blame] | 144 | /* GNB IOAPIC resource */ |
Arthur Heymans | 61daf9b | 2023-06-15 09:59:58 +0200 | [diff] [blame] | 145 | mmio_range(dev, IOMMU_IOAPIC_IDX, GNB_IO_APIC_ADDR, 0x1000); |
Felix Held | dafc619 | 2022-11-10 18:19:36 +0100 | [diff] [blame] | 146 | |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 147 | /* Reserve fixed IOMMU MMIO region */ |
| 148 | mmio_range(dev, idx++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); |
| 149 | |
Felix Held | 2e81436 | 2022-11-10 22:44:18 +0100 | [diff] [blame] | 150 | if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) { |
| 151 | printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 152 | return; |
| 153 | } |
| 154 | |
Felix Held | 2e81436 | 2022-11-10 22:44:18 +0100 | [diff] [blame] | 155 | while (fsp_hob_iterator_get_next_resource(&hob_iterator, &res) == CB_SUCCESS) { |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 156 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) |
| 157 | continue; /* 0 through low usable was set above */ |
| 158 | if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) |
| 159 | continue; /* Done separately */ |
| 160 | |
| 161 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 162 | ram_range(dev, idx++, res->addr, res->length); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 163 | else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) |
Arthur Heymans | b2de1a3 | 2023-07-05 12:15:51 +0200 | [diff] [blame] | 164 | reserved_ram_range(dev, idx++, res->addr, res->length); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 165 | else |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 166 | printk(BIOS_ERR, "failed to set resources for type %d\n", |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 167 | res->type); |
| 168 | } |
| 169 | } |
| 170 | |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 171 | static void root_complex_init(struct device *dev) |
| 172 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 173 | register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 174 | } |
| 175 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 176 | static void acipgen_dptci(void) |
| 177 | { |
Felix Held | 507fc03 | 2020-12-05 01:55:27 +0100 | [diff] [blame] | 178 | const struct soc_amd_picasso_config *config = config_of_soc(); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 179 | |
Tim Van Patten | 54ce4aa | 2022-09-13 14:37:32 -0600 | [diff] [blame] | 180 | /* Normal mode DPTC values. */ |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 181 | struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, |
| 182 | config->sustained_power_limit_mW, |
| 183 | config->fast_ppt_limit_mW, |
| 184 | config->slow_ppt_limit_mW); |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 185 | acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); |
| 186 | |
| 187 | /* Tablet Mode */ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 188 | struct dptc_input tablet_mode_input = DPTC_INPUTS( |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 189 | config->thermctl_limit_tablet_mode_degreeC, |
| 190 | config->sustained_power_limit_tablet_mode_mW, |
| 191 | config->fast_ppt_limit_tablet_mode_mW, |
| 192 | config->slow_ppt_limit_tablet_mode_mW); |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 193 | acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input, |
| 194 | sizeof(tablet_mode_input)); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 195 | } |
| 196 | |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 197 | static void root_complex_fill_ssdt(const struct device *device) |
| 198 | { |
Tim Van Patten | 54ce4aa | 2022-09-13 14:37:32 -0600 | [diff] [blame] | 199 | if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) |
| 200 | acipgen_dptci(); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 201 | } |
| 202 | |
Felix Held | ff092d4 | 2021-02-17 00:04:59 +0100 | [diff] [blame] | 203 | static const char *gnb_acpi_name(const struct device *dev) |
| 204 | { |
| 205 | return "GNB"; |
| 206 | } |
| 207 | |
Arthur Heymans | 826955d | 2022-09-20 17:26:30 +0200 | [diff] [blame] | 208 | struct device_operations picasso_root_complex_operations = { |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 209 | .read_resources = read_resources, |
Felix Held | 9541d17 | 2021-01-05 00:56:10 +0100 | [diff] [blame] | 210 | .set_resources = noop_set_resources, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 211 | .enable_resources = pci_dev_enable_resources, |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 212 | .init = root_complex_init, |
Felix Held | ff092d4 | 2021-02-17 00:04:59 +0100 | [diff] [blame] | 213 | .acpi_name = gnb_acpi_name, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 214 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
| 215 | }; |
Felix Held | 43662b5 | 2023-07-18 20:36:34 +0200 | [diff] [blame^] | 216 | |
| 217 | uint32_t get_iohc_misc_smn_base(struct device *domain) |
| 218 | { |
| 219 | return 0x13b10000; |
| 220 | } |
| 221 | |
| 222 | static const struct non_pci_mmio_reg non_pci_mmio[] = { |
| 223 | { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 224 | { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 225 | /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we |
| 226 | tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB |
| 227 | resource. */ |
| 228 | { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, |
| 229 | { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 230 | { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 231 | { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 232 | { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 233 | }; |
| 234 | |
| 235 | const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) |
| 236 | { |
| 237 | *count = ARRAY_SIZE(non_pci_mmio); |
| 238 | return non_pci_mmio; |
| 239 | } |