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review.coreboot.org / coreboot / bc45650b5fba1da8214687aaef36b60a1fa19a6c / . / src / soc / amd / picasso / root_complex.c
blob: 4930a0e87f40be7f71f92cf7f9d8598c66c22da2 [file] [log] [blame]
Marshall Dawsoneb724872019-07-16 15:46:35 -0600[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <acpi/acpigen.h>
4#include <cbmem.h>
5#include <console/console.h>
6#include <cpu/amd/msr.h>
7#include <cpu/amd/mtrr.h>
8#include <device/device.h>
9#include <device/pci.h>
10#include <device/pci_ids.h>
11#include <fsp/util.h>
12#include <stdint.h>
Furquan Shaikhbc456502020-06-10 16:37:23 -0700[diff] [blame^]13#include <soc/memmap.h>
Marshall Dawsoneb724872019-07-16 15:46:35 -0600[diff] [blame]14
Furquan Shaikhbc456502020-06-10 16:37:23 -0700[diff] [blame^]15/*
16 *
17 * +--------------------------------+
18 * | |
19 * | |
20 * | |
21 * | |
22 * | |
23 * | |
24 * | |
25 * reserved_dram_end +--------------------------------+
26 * | |
27 * | verstage (if reqd) |
28 * | (VERSTAGE_SIZE) |
29 * +--------------------------------+ VERSTAGE_ADDR
30 * | |
31 * | FSP-M |
32 * | (FSP_M_SIZE) |
33 * +--------------------------------+ FSP_M_ADDR
34 * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10
35 * | romstage |
36 * | (ROMSTAGE_SIZE) |
37 * +--------------------------------+ ROMSTAGE_ADDR
38 * | bootblock |
39 * | (C_ENV_BOOTBLOCK_SIZE) |
40 * +--------------------------------+ BOOTBLOCK_ADDR
41 * | Unused hole |
42 * | (86KiB) |
43 * +--------------------------------+
44 * | FMAP cache (FMAP_SIZE) |
45 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
46 * | Early Timestamp region (512B) |
47 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
48 * | Preram CBMEM console |
49 * | (PRERAM_CBMEM_CONSOLE_SIZE) |
50 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
51 * | PSP shared (vboot workbuf) |
52 * | (PSP_SHAREDMEM_SIZE) |
53 * +--------------------------------+ PSP_SHAREDMEM_BASE
54 * | APOB (64KiB) |
55 * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
56 * | Early BSP stack |
57 * | (EARLYRAM_BSP_STACK_SIZE) |
58 * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
59 * | DRAM |
60 * +--------------------------------+ 0x100000
61 * | Option ROM |
62 * +--------------------------------+ 0xc0000
63 * | Legacy VGA |
64 * +--------------------------------+ 0xa0000
65 * | DRAM |
66 * +--------------------------------+ 0x0
67 */
Marshall Dawsoneb724872019-07-16 15:46:35 -0600[diff] [blame]68static void read_resources(struct device *dev)
69{
70 uint32_t mem_usable = (uintptr_t)cbmem_top();
71 unsigned int idx = 0;
72 const struct hob_header *hob = fsp_get_hob_list();
73 const struct hob_resource *res;
74
Furquan Shaikhbc456502020-06-10 16:37:23 -0700[diff] [blame^]75 uintptr_t early_reserved_dram_start, early_reserved_dram_end;
76 const struct memmap_early_dram *e = memmap_get_early_dram_usage();
77
78 early_reserved_dram_start = e->base;
79 early_reserved_dram_end = e->base + e->size;
80
Marshall Dawsoneb724872019-07-16 15:46:35 -0600[diff] [blame]81 /* 0x0 - 0x9ffff */
82 ram_resource(dev, idx++, 0, 0xa0000 / KiB);
83
84 /* 0xa0000 - 0xbffff: legacy VGA */
85 mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
86
87 /* 0xc0000 - 0xfffff: Option ROM */
88 reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
89
Furquan Shaikhbc456502020-06-10 16:37:23 -0700[diff] [blame^]90 /* 1MB - bottom of DRAM reserved for early coreboot usage */
91 ram_resource(dev, idx++, (1 * MiB) / KiB,
92 (early_reserved_dram_start - (1 * MiB)) / KiB);
93
94 /* DRAM reserved for early coreboot usage */
95 reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
96 (early_reserved_dram_end - early_reserved_dram_start) / KiB);
97
98 /* top of DRAM consumed early - low top usable RAM
99 * cbmem_top() accounts for low UMA and TSEG if they are used. */
100 ram_resource(dev, idx++, early_reserved_dram_end / KiB,
101 (mem_usable - early_reserved_dram_end) / KiB);
Marshall Dawsoneb724872019-07-16 15:46:35 -0600[diff] [blame]102
103 mmconf_resource(dev, MMIO_CONF_BASE);
104
105 if (!hob) {
106 printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n",
107 __func__);
108 return;
109 }
110
111 for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
112
113 if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
114 continue;
115
116 res = fsp_hob_header_to_resource(hob);
117
118 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
119 continue; /* 0 through low usable was set above */
120 if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
121 continue; /* Done separately */
122
123 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
124 ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
125 else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
126 reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
127 else
128 printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
129 res->type);
130 }
131}
132
133/* Used by \_SB.PCI0._CRS */
134static void root_complex_fill_ssdt(const struct device *device)
135{
136 msr_t msr;
137
138 acpigen_write_scope(acpi_device_scope(device));
139
140 msr = rdmsr(TOP_MEM);
141 acpigen_write_name_dword("TOM1", msr.lo);
142 msr = rdmsr(TOP_MEM2);
143 /*
144 * Since XP only implements parts of ACPI 2.0, we can't use a qword
145 * here.
146 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
147 * slide 22ff.
148 * Shift value right by 20 bit to make it fit into 32bit,
149 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
150 */
151 acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
152 acpigen_pop_len();
153}
154
155static struct device_operations root_complex_operations = {
156 .read_resources = read_resources,
157 .enable_resources = pci_dev_enable_resources,
158 .acpi_fill_ssdt = root_complex_fill_ssdt,
159};
160
161static const struct pci_driver family17_root_complex __pci_driver = {
162 .ops = &root_complex_operations,
163 .vendor = PCI_VENDOR_ID_AMD,
164 .device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB,
165};