Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/x86/msr.h> |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 6 | #include <cpu/intel/cpu_ids.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
Tim Wawrzynczak | 6f73a20 | 2022-02-04 12:45:37 -0700 | [diff] [blame] | 8 | #include <drivers/wifi/generic/wifi.h> |
Tarun Tuli | eed31cb | 2023-01-31 18:14:35 +0000 | [diff] [blame] | 9 | #include <elog.h> |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 10 | #include <fsp/fsp_debug_event.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 11 | #include <fsp/util.h> |
Dinesh Gehlot | d910fec | 2022-12-25 13:00:04 +0000 | [diff] [blame] | 12 | #include <gpio.h> |
Sridhar Siricilla | dddaeed | 2022-04-28 23:34:14 +0530 | [diff] [blame] | 13 | #include <intelbasecode/debug_feature.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 14 | #include <intelblocks/cpulib.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 15 | #include <intelblocks/pcie_rp.h> |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 16 | #include <option.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 17 | #include <soc/iomap.h> |
| 18 | #include <soc/msr.h> |
| 19 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 20 | #include <soc/pcie.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 21 | #include <soc/romstage.h> |
| 22 | #include <soc/soc_chip.h> |
| 23 | #include <string.h> |
| 24 | |
Jeremy Compostella | e3884a1 | 2023-01-19 11:41:30 -0700 | [diff] [blame] | 25 | #include "ux.h" |
| 26 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 27 | #define FSP_CLK_NOTUSED 0xFF |
| 28 | #define FSP_CLK_LAN 0x70 |
| 29 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 30 | |
| 31 | #define CPU_PCIE_BASE 0x40 |
| 32 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 33 | enum vtd_base_index_type { |
| 34 | VTD_GFX, |
| 35 | VTD_IPU, |
| 36 | VTD_VTVCO, |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 37 | VTD_TBT0, |
| 38 | VTD_TBT1, |
| 39 | VTD_TBT2, |
| 40 | VTD_TBT3, |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 41 | }; |
| 42 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 43 | static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) |
| 44 | { |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 45 | assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 46 | |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 47 | if (type == PCIE_RP_PCH) |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 48 | return rp_number; |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 49 | else // type == PCIE_RP_CPU |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 50 | return CPU_PCIE_BASE + rp_number; |
| 51 | } |
| 52 | |
| 53 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type, |
| 54 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 55 | { |
| 56 | size_t i; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 57 | /* bitmask to save the status of clkreq assignment */ |
| 58 | static unsigned int clk_req_mapping = 0; |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 59 | |
| 60 | for (i = 0; i < cfg_count; i++) { |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 61 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { |
| 62 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 63 | continue; |
| 64 | } |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 65 | if (!(en_mask & BIT(i))) |
| 66 | continue; |
| 67 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 68 | continue; |
Cliff Huang | edf71a0 | 2022-04-28 18:55:48 -0700 | [diff] [blame] | 69 | if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { |
| 70 | printk(BIOS_WARNING, "Missing root port clock structure definition\n"); |
| 71 | continue; |
| 72 | } |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 73 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 74 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 75 | , cfg[i].clk_req); |
| 76 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 77 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 78 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 79 | } |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 80 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); |
| 81 | } |
| 82 | } |
| 83 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 84 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 85 | const struct soc_intel_alderlake_config *config) |
| 86 | { |
| 87 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 88 | unsigned int i; |
| 89 | |
| 90 | for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { |
| 91 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 92 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 93 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 94 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 95 | else |
| 96 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 97 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 98 | } |
| 99 | |
| 100 | /* Configure PCH PCIE ports */ |
| 101 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 102 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 103 | CONFIG_MAX_PCH_ROOT_PORTS); |
| 104 | |
| 105 | /* Configure CPU PCIE ports */ |
| 106 | m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 107 | pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 108 | CONFIG_MAX_CPU_ROOT_PORTS); |
| 109 | } |
| 110 | |
| 111 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 112 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 113 | { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 114 | unsigned int i; |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 115 | const struct ddi_port_upds { |
| 116 | uint8_t *ddc; |
| 117 | uint8_t *hpd; |
| 118 | } ddi_port_upds[] = { |
| 119 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 120 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 121 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 122 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 123 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 124 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 125 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 126 | }; |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 127 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 128 | if (m_cfg->InternalGfx) { |
| 129 | /* IGD is enabled, set IGD stolen size to 60MB. */ |
| 130 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; |
| 131 | /* DP port config */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 132 | m_cfg->DdiPortAConfig = config->ddi_portA_config; |
| 133 | m_cfg->DdiPortBConfig = config->ddi_portB_config; |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 134 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 135 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 136 | DDI_ENABLE_DDC); |
| 137 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 138 | DDI_ENABLE_HPD); |
| 139 | } |
| 140 | } else { |
| 141 | /* IGD is disabled, skip IGD init in FSP. */ |
| 142 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 143 | /* DP port config */ |
| 144 | m_cfg->DdiPortAConfig = 0; |
| 145 | m_cfg->DdiPortBConfig = 0; |
| 146 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 147 | *ddi_port_upds[i].ddc = 0; |
| 148 | *ddi_port_upds[i].hpd = 0; |
| 149 | } |
| 150 | } |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 151 | } |
| 152 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 153 | const struct soc_intel_alderlake_config *config) |
| 154 | { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 155 | m_cfg->SaGv = config->sagv; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 156 | m_cfg->RMT = config->RMT; |
Franklin Lin | 759bb4c | 2022-07-15 17:53:13 +0800 | [diff] [blame] | 157 | if (config->max_dram_speed_mts) { |
Scott Chao | ab638c1 | 2022-04-20 15:16:06 +0800 | [diff] [blame] | 158 | m_cfg->DdrFreqLimit = config->max_dram_speed_mts; |
Franklin Lin | 759bb4c | 2022-07-15 17:53:13 +0800 | [diff] [blame] | 159 | m_cfg->DdrSpeedControl = 1; |
| 160 | } |
Bora Guvendik | 433343e | 2023-04-24 15:50:15 -0700 | [diff] [blame^] | 161 | #if CONFIG(SOC_INTEL_RAPTORLAKE) |
| 162 | m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; |
| 163 | #endif |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 164 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 165 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 166 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 167 | const struct soc_intel_alderlake_config *config) |
| 168 | { |
| 169 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 170 | /* CpuRatio Settings */ |
| 171 | if (config->cpu_ratio_override) |
| 172 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 173 | else |
| 174 | /* Set CpuRatio to match existing MSR value */ |
| 175 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 176 | |
Subrata Banik | 80835a1 | 2020-09-23 17:46:11 +0530 | [diff] [blame] | 177 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 178 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 179 | m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 183 | const struct soc_intel_alderlake_config *config) |
| 184 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 185 | /* Disable BIOS Guard */ |
| 186 | m_cfg->BiosGuard = 0; |
Subrata Banik | 1e71fe1 | 2022-08-15 15:40:59 +0530 | [diff] [blame] | 187 | m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 188 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 189 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 190 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 191 | const struct soc_intel_alderlake_config *config) |
| 192 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 193 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 194 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 195 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 196 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 197 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 198 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 199 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 200 | const struct soc_intel_alderlake_config *config) |
| 201 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 202 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 203 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 204 | /* IPU */ |
| 205 | m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); |
| 206 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 207 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 208 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 209 | const struct soc_intel_alderlake_config *config) |
| 210 | { |
| 211 | m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); |
| 212 | } |
| 213 | |
| 214 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 215 | const struct soc_intel_alderlake_config *config) |
| 216 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 217 | /* Disable Lock PCU Thermal Management registers */ |
| 218 | m_cfg->LockPTMregs = 0; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 219 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 220 | /* Skip CPU replacement check */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 221 | m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 222 | |
| 223 | /* Skip GPIO configuration from FSP */ |
| 224 | m_cfg->GpioOverride = 0x1; |
MAULIK V VAGHELA | 9a7fbbc | 2021-10-13 11:52:17 +0530 | [diff] [blame] | 225 | |
Ronak Kanabar | fc69b9d | 2021-10-06 13:02:34 +0530 | [diff] [blame] | 226 | /* CNVi DDR RFI Mitigation */ |
Tim Wawrzynczak | 6f73a20 | 2022-02-04 12:45:37 -0700 | [diff] [blame] | 227 | const struct device_path path[] = { |
| 228 | { .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_CNVI_WIFI }, |
| 229 | { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; |
| 230 | const struct device *dev = find_dev_nested_path(pci_root_bus(), path, |
| 231 | ARRAY_SIZE(path)); |
| 232 | if (is_dev_enabled(dev)) |
| 233 | m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); |
V Sowmya | 2bc54e7 | 2022-08-04 22:50:51 +0530 | [diff] [blame] | 234 | |
| 235 | /* Skip MBP HOB */ |
Kapil Porwal | 23ef60d | 2023-01-16 16:07:48 +0000 | [diff] [blame] | 236 | m_cfg->SkipMbpHob = !CONFIG(FSP_PUBLISH_MBP_HOB); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 240 | const struct soc_intel_alderlake_config *config) |
| 241 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 242 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 243 | m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 244 | m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; |
| 245 | m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; |
| 246 | m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; |
| 247 | m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; |
Sean Rhodes | 7bfc256 | 2023-01-06 10:50:53 +0000 | [diff] [blame] | 248 | m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable; |
Furquan Shaikh | c1c1ba5 | 2021-04-20 16:57:59 -0700 | [diff] [blame] | 249 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 250 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 251 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 252 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 253 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 254 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 255 | const struct soc_intel_alderlake_config *config) |
| 256 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 257 | m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 258 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 259 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 260 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 261 | const struct soc_intel_alderlake_config *config) |
| 262 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 263 | /* Tcss USB */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 264 | m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI); |
| 265 | m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 266 | |
| 267 | /* TCSS DMA */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 268 | m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); |
| 269 | m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); |
Kane Chen | 8327a7e | 2022-09-27 09:54:30 +0800 | [diff] [blame] | 270 | |
| 271 | #if CONFIG(SOC_INTEL_RAPTORLAKE) |
| 272 | m_cfg->DisableDynamicTccoldHandshake = |
| 273 | config->disable_dynamic_tccold_handshake; |
| 274 | #endif |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 275 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 276 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 277 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 278 | const struct soc_intel_alderlake_config *config) |
| 279 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 280 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0); |
| 281 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1); |
| 282 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); |
| 283 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 284 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 285 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 286 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 287 | const struct soc_intel_alderlake_config *config) |
| 288 | { |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 289 | const uint32_t cpuid = cpu_get_cpuid(); |
| 290 | |
| 291 | /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ |
Lean Sheng Tan | 9e78dd1 | 2022-04-01 12:03:51 +0200 | [diff] [blame] | 292 | if (cpuid == CPUID_ALDERLAKE_J0 || cpuid == CPUID_ALDERLAKE_Q0) { |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 293 | m_cfg->VtdDisable = 1; |
| 294 | return; |
| 295 | } |
| 296 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 297 | m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; |
| 298 | m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; |
| 299 | m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; |
| 300 | |
| 301 | m_cfg->VtdDisable = 0; |
| 302 | m_cfg->VtdIopEnable = !m_cfg->VtdDisable; |
| 303 | m_cfg->VtdIgdEnable = m_cfg->InternalGfx; |
| 304 | m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; |
| 305 | |
Michał Żygowski | c7fee24 | 2022-10-15 16:39:46 +0200 | [diff] [blame] | 306 | m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION); |
| 307 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 308 | if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { |
| 309 | m_cfg->VtdIgdEnable = 0; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 310 | printk(BIOS_ERR, "Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 311 | } |
| 312 | |
| 313 | if (m_cfg->VtdIpuEnable && m_cfg->VtdBaseAddress[VTD_IPU] == 0) { |
| 314 | m_cfg->VtdIpuEnable = 0; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 315 | printk(BIOS_ERR, "Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | if (!m_cfg->VtdDisable && m_cfg->VtdBaseAddress[VTD_VTVCO] == 0) { |
| 319 | m_cfg->VtdDisable = 1; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 320 | printk(BIOS_ERR, "Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 321 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 322 | |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 323 | if (m_cfg->TcssDma0En || m_cfg->TcssDma1En) |
| 324 | m_cfg->VtdItbtEnable = 1; |
| 325 | |
| 326 | if (m_cfg->TcssItbtPcie0En) |
| 327 | m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS; |
| 328 | |
| 329 | if (m_cfg->TcssItbtPcie1En) |
| 330 | m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS; |
| 331 | |
| 332 | if (m_cfg->TcssItbtPcie2En) |
| 333 | m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS; |
| 334 | |
| 335 | if (m_cfg->TcssItbtPcie3En) |
| 336 | m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS; |
| 337 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 338 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 339 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 340 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 341 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 342 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 343 | const struct soc_intel_alderlake_config *config) |
| 344 | { |
| 345 | /* Set debug probe type */ |
| 346 | m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; |
Francois Toguo | cea4f92 | 2021-04-16 21:20:39 -0700 | [diff] [blame] | 347 | |
| 348 | /* CrashLog config */ |
Subrata Banik | 7b8d11b | 2021-07-14 13:11:53 +0530 | [diff] [blame] | 349 | m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); |
| 350 | m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 351 | } |
| 352 | |
Maximilian Brune | 2c98488 | 2022-10-24 20:31:18 +0200 | [diff] [blame] | 353 | static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, |
| 354 | const struct soc_intel_alderlake_config *config) |
| 355 | { |
| 356 | /* In-Band ECC configuration */ |
| 357 | if (config->ibecc.enable) { |
| 358 | m_cfg->Ibecc = config->ibecc.enable; |
| 359 | m_cfg->IbeccOperationMode = config->ibecc.mode; |
| 360 | if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { |
| 361 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, |
| 362 | config->ibecc.range_enable); |
| 363 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase, |
| 364 | config->ibecc.range_base); |
| 365 | FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask, |
| 366 | config->ibecc.range_mask); |
| 367 | } |
| 368 | } |
| 369 | } |
| 370 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 371 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 372 | const struct soc_intel_alderlake_config *config) |
| 373 | { |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 374 | void (*const fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 375 | const struct soc_intel_alderlake_config *config) = { |
| 376 | fill_fspm_igd_params, |
| 377 | fill_fspm_mrc_params, |
| 378 | fill_fspm_cpu_params, |
| 379 | fill_fspm_security_params, |
| 380 | fill_fspm_uart_params, |
| 381 | fill_fspm_ipu_params, |
| 382 | fill_fspm_smbus_params, |
| 383 | fill_fspm_misc_params, |
| 384 | fill_fspm_audio_params, |
| 385 | fill_fspm_pcie_rp_params, |
| 386 | fill_fspm_ish_params, |
| 387 | fill_fspm_tcss_params, |
| 388 | fill_fspm_usb4_params, |
| 389 | fill_fspm_vtd_params, |
| 390 | fill_fspm_trace_params, |
Maximilian Brune | 2c98488 | 2022-10-24 20:31:18 +0200 | [diff] [blame] | 391 | fill_fspm_ibecc_params, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 392 | }; |
| 393 | |
| 394 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 395 | fill_fspm_params[i](m_cfg, config); |
| 396 | } |
| 397 | |
Sridhar Siricilla | dddaeed | 2022-04-28 23:34:14 +0530 | [diff] [blame] | 398 | static void debug_override_memory_init_params(FSP_M_CONFIG *mupd) |
| 399 | { |
| 400 | debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode); |
| 401 | } |
| 402 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 403 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 404 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 405 | const struct soc_intel_alderlake_config *config; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 406 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 407 | FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; |
| 408 | |
Subrata Banik | 88381c9 | 2022-03-29 11:26:11 +0530 | [diff] [blame] | 409 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { |
| 410 | if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { |
| 411 | enum fsp_log_level log_level = fsp_map_console_log_level(); |
| 412 | arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 413 | fsp_debug_event_handler); |
| 414 | /* Set Serial debug message level */ |
| 415 | m_cfg->PcdSerialDebugLevel = log_level; |
| 416 | /* Set MRC debug level */ |
| 417 | m_cfg->SerialDebugMrcLevel = log_level; |
| 418 | } else { |
| 419 | /* Disable Serial debug message */ |
| 420 | m_cfg->PcdSerialDebugLevel = 0; |
| 421 | /* Disable MRC debug message */ |
| 422 | m_cfg->SerialDebugMrcLevel = 0; |
| 423 | } |
| 424 | } |
Jeremy Compostella | 1f4d7c7 | 2023-01-04 09:41:52 -0700 | [diff] [blame] | 425 | |
| 426 | /* |
| 427 | * If valid MRC cache data is not found, FSP should perform a memory |
| 428 | * training. Memory training can take a while so let's inform the end |
| 429 | * user with an on-screen text message. |
| 430 | */ |
Tarun Tuli | eed31cb | 2023-01-31 18:14:35 +0000 | [diff] [blame] | 431 | if (!arch_upd->NvsBufferPtr) { |
| 432 | if (ux_inform_user_of_update_operation("memory training")) |
| 433 | elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); |
| 434 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 435 | config = config_of_soc(); |
| 436 | |
| 437 | soc_memory_init_params(m_cfg, config); |
Zhuohao Lee | 09f3b6c | 2022-01-20 21:30:12 +0800 | [diff] [blame] | 438 | mainboard_memory_init_params(mupd); |
Sridhar Siricilla | dddaeed | 2022-04-28 23:34:14 +0530 | [diff] [blame] | 439 | |
| 440 | /* Override the memory init params through runtime debug capability */ |
| 441 | if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) |
| 442 | debug_override_memory_init_params(m_cfg); |
Jeremy Compostella | 9df1197 | 2022-12-02 10:59:49 -0700 | [diff] [blame] | 443 | |
| 444 | if (CONFIG(HWBASE_STATIC_MMIO)) |
| 445 | m_cfg->GttMmAdr = CONFIG_GFX_GMA_DEFAULT_MMIO; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 446 | } |
| 447 | |
Zhuohao Lee | 09f3b6c | 2022-01-20 21:30:12 +0800 | [diff] [blame] | 448 | __weak void mainboard_memory_init_params(FSPM_UPD *memupd) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 449 | { |
| 450 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 451 | } |