Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2 | |
Edward O'Callaghan | a34a1da | 2014-06-01 16:09:21 +1000 | [diff] [blame] | 3 | #ifndef NORTHBRIDGE_INTEL_I945_H |
| 4 | #define NORTHBRIDGE_INTEL_I945_H |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 6 | #define DEFAULT_X60BAR 0xfed13000 |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 7 | |
Antonello Dettori | a1e1e5c | 2016-08-21 10:51:53 +0200 | [diff] [blame] | 8 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 9 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 10 | /* Everything below this line is ignored in the DSDT */ |
| 11 | #ifndef __ACPI__ |
| 12 | |
Denis 'GNUtoo' Carikli | 7ed7394 | 2013-05-26 23:56:43 +0200 | [diff] [blame] | 13 | /* Display defines for the interrupt 15h handler */ |
| 14 | #define INT15_5F35_CL_DISPLAY_DEFAULT 0 |
| 15 | #define INT15_5F35_CL_DISPLAY_CRT (1 << 0) |
| 16 | #define INT15_5F35_CL_DISPLAY_TV (1 << 1) |
| 17 | #define INT15_5F35_CL_DISPLAY_EFP (1 << 2) |
| 18 | #define INT15_5F35_CL_DISPLAY_LCD (1 << 3) |
| 19 | #define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4) |
| 20 | #define INT15_5F35_CL_DISPLAY_TV2 (1 << 5) |
| 21 | #define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6) |
| 22 | #define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) |
| 23 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 24 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 25 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | |
| 27 | #define EPBAR 0x40 |
| 28 | #define MCHBAR 0x44 |
| 29 | #define PCIEXBAR 0x48 |
| 30 | #define DMIBAR 0x4c |
| 31 | #define X60BAR 0x60 |
| 32 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 33 | #define GGC 0x52 /* GMCH Graphics Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 34 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 35 | #define DEVEN 0x54 /* Device Enable */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 36 | #define DEVEN_D0F0 (1 << 0) |
| 37 | #define DEVEN_D1F0 (1 << 1) |
| 38 | #define DEVEN_D2F0 (1 << 3) |
| 39 | #define DEVEN_D2F1 (1 << 4) |
Edward O'Callaghan | a34a1da | 2014-06-01 16:09:21 +1000 | [diff] [blame] | 40 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 41 | #ifndef BOARD_DEVEN |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 42 | #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) |
Edward O'Callaghan | a34a1da | 2014-06-01 16:09:21 +1000 | [diff] [blame] | 43 | #endif /* BOARD_DEVEN */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 44 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 45 | #define PAM0 0x90 |
| 46 | #define PAM1 0x91 |
| 47 | #define PAM2 0x92 |
| 48 | #define PAM3 0x93 |
| 49 | #define PAM4 0x94 |
| 50 | #define PAM5 0x95 |
| 51 | #define PAM6 0x96 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 53 | #define LAC 0x97 /* Legacy Access Control */ |
| 54 | #define TOLUD 0x9c /* Top of Low Used Memory */ |
| 55 | #define SMRAM 0x9d /* System Management RAM Control */ |
Elyes HAOUAS | 8324d87 | 2018-01-19 12:52:25 +0100 | [diff] [blame] | 56 | #define ESMRAMC 0x9e /* Extended System Management RAM Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 57 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 58 | #define TOM 0xa0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 59 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 60 | #define SKPAD 0xdc /* Scratchpad Data */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 61 | |
| 62 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 63 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 64 | #define PCISTS1 0x06 /* 16bit */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 65 | #define SSTS1 0x1e /* 16bit */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 66 | #define PEG_CAP 0xa2 /* 16bit */ |
| 67 | #define DSTS 0xaa /* 16bit */ |
| 68 | #define SLOTCAP 0xb4 /* 32bit */ |
| 69 | #define SLOTSTS 0xba /* 16bit */ |
| 70 | #define PEG_LC 0xec /* 32bit */ |
| 71 | #define PVCCAP1 0x104 /* 32bit */ |
| 72 | #define VC0RCTL 0x114 /* 32bit */ |
| 73 | #define LE1D 0x150 /* 32bit */ |
| 74 | #define LE1A 0x158 /* 64bit */ |
| 75 | #define UESTS 0x1c4 /* 32bit */ |
| 76 | #define CESTS 0x1d0 /* 32bit */ |
| 77 | #define PEGTC 0x204 /* 32bit */ |
| 78 | #define PEGCC 0x208 /* 32bit */ |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 79 | #define PEGSTS 0x214 /* 32bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 80 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 81 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 82 | #define IGD_DEV PCI_DEV(0, 2, 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | |
Paul Menzel | d235da1 | 2014-06-03 00:15:30 +0200 | [diff] [blame] | 84 | #define GMADR 0x18 |
| 85 | #define GTTADR 0x1c |
Paul Menzel | 5068463 | 2014-06-03 00:26:03 +0200 | [diff] [blame] | 86 | #define BSM 0x5c |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 87 | #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 88 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | /* |
| 90 | * MCHBAR |
| 91 | */ |
| 92 | |
Angel Pons | 4299cb4 | 2021-01-20 12:32:22 +0100 | [diff] [blame] | 93 | #include <northbridge/intel/common/fixed_bars.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 94 | |
| 95 | /* Chipset Control Registers */ |
| 96 | #define FSBPMC3 0x40 /* 32bit */ |
| 97 | #define FSBPMC4 0x44 /* 32bit */ |
| 98 | #define FSBSNPCTL 0x48 /* 32bit */ |
| 99 | #define SLPCTL 0x90 /* 32bit */ |
| 100 | |
| 101 | #define C0DRB0 0x100 /* 8bit */ |
| 102 | #define C0DRB1 0x101 /* 8bit */ |
| 103 | #define C0DRB2 0x102 /* 8bit */ |
| 104 | #define C0DRB3 0x103 /* 8bit */ |
| 105 | #define C0DRA0 0x108 /* 8bit */ |
| 106 | #define C0DRA2 0x109 /* 8bit */ |
| 107 | #define C0DCLKDIS 0x10c /* 8bit */ |
| 108 | #define C0BNKARC 0x10e /* 16bit */ |
| 109 | #define C0DRT0 0x110 /* 32bit */ |
| 110 | #define C0DRT1 0x114 /* 32bit */ |
| 111 | #define C0DRT2 0x118 /* 32bit */ |
| 112 | #define C0DRT3 0x11c /* 32bit */ |
| 113 | #define C0DRC0 0x120 /* 32bit */ |
| 114 | #define C0DRC1 0x124 /* 32bit */ |
| 115 | #define C0DRC2 0x128 /* 32bit */ |
| 116 | #define C0AIT 0x130 /* 64bit */ |
| 117 | #define C0DCCFT 0x138 /* 64bit */ |
| 118 | #define C0GTEW 0x140 /* 32bit */ |
| 119 | #define C0GTC 0x144 /* 32bit */ |
| 120 | #define C0DTPEW 0x148 /* 64bit */ |
| 121 | #define C0DTAEW 0x150 /* 64bit */ |
| 122 | #define C0DTC 0x158 /* 32bit */ |
| 123 | #define C0DMC 0x164 /* 32bit */ |
| 124 | #define C0ODT 0x168 /* 64bit */ |
| 125 | |
| 126 | #define C1DRB0 0x180 /* 8bit */ |
| 127 | #define C1DRB1 0x181 /* 8bit */ |
| 128 | #define C1DRB2 0x182 /* 8bit */ |
| 129 | #define C1DRB3 0x183 /* 8bit */ |
| 130 | #define C1DRA0 0x188 /* 8bit */ |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 131 | #define C1DRA2 0x189 /* 8bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 132 | #define C1DCLKDIS 0x18c /* 8bit */ |
| 133 | #define C1BNKARC 0x18e /* 16bit */ |
| 134 | #define C1DRT0 0x190 /* 32bit */ |
| 135 | #define C1DRT1 0x194 /* 32bit */ |
| 136 | #define C1DRT2 0x198 /* 32bit */ |
| 137 | #define C1DRT3 0x19c /* 32bit */ |
| 138 | #define C1DRC0 0x1a0 /* 32bit */ |
| 139 | #define C1DRC1 0x1a4 /* 32bit */ |
| 140 | #define C1DRC2 0x1a8 /* 32bit */ |
| 141 | #define C1AIT 0x1b0 /* 64bit */ |
| 142 | #define C1DCCFT 0x1b8 /* 64bit */ |
| 143 | #define C1GTEW 0x1c0 /* 32bit */ |
| 144 | #define C1GTC 0x1c4 /* 32bit */ |
| 145 | #define C1DTPEW 0x1c8 /* 64bit */ |
| 146 | #define C1DTAEW 0x1d0 /* 64bit */ |
| 147 | #define C1DTC 0x1d8 /* 32bit */ |
| 148 | #define C1DMC 0x1e4 /* 32bit */ |
| 149 | #define C1ODT 0x1e8 /* 64bit */ |
| 150 | |
| 151 | #define DCC 0x200 /* 32bit */ |
| 152 | #define CCCFT 0x208 /* 64bit */ |
| 153 | #define WCC 0x218 /* 32bit */ |
| 154 | #define MMARB0 0x220 /* 32bit */ |
| 155 | #define MMARB1 0x224 /* 32bit */ |
| 156 | #define SBTEST 0x230 /* 32bit */ |
| 157 | #define SBOCC 0x238 /* 32bit */ |
| 158 | #define ODTC 0x284 /* 32bit */ |
| 159 | #define SMVREFC 0x2a0 /* 32bit */ |
| 160 | #define DRTST 0x2a8 /* 32bit */ |
| 161 | #define REPC 0x2e0 /* 32bit */ |
| 162 | #define DQSMT 0x2f4 /* 16bit */ |
| 163 | #define RCVENMT 0x2f8 /* 32bit */ |
| 164 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 165 | #define C0R0B00DQST 0x300 /* 64bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 166 | |
| 167 | #define C0WL0REOST 0x340 /* 8bit */ |
| 168 | #define C0WL1REOST 0x341 /* 8bit */ |
| 169 | #define C0WL2REOST 0x342 /* 8bit */ |
| 170 | #define C0WL3REOST 0x343 /* 8bit */ |
| 171 | #define WDLLBYPMODE 0x360 /* 16bit */ |
| 172 | #define C0WDLLCMC 0x36c /* 32bit */ |
| 173 | #define C0HCTC 0x37c /* 8bit */ |
| 174 | |
Uwe Hermann | a163729 | 2008-11-09 10:57:26 +0000 | [diff] [blame] | 175 | #define C1R0B00DQST 0x380 /* 64bit */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 176 | |
| 177 | #define C1WL0REOST 0x3c0 /* 8bit */ |
| 178 | #define C1WL1REOST 0x3c1 /* 8bit */ |
| 179 | #define C1WL2REOST 0x3c2 /* 8bit */ |
| 180 | #define C1WL3REOST 0x3c3 /* 8bit */ |
| 181 | #define C1WDLLCMC 0x3ec /* 32bit */ |
| 182 | #define C1HCTC 0x3fc /* 8bit */ |
| 183 | |
| 184 | #define GBRCOMPCTL 0x400 /* 32bit */ |
| 185 | |
| 186 | #define SMSRCTL 0x408 /* XXX who knows */ |
| 187 | #define C0DRAMW 0x40c /* 16bit */ |
| 188 | #define G1SC 0x410 /* 8bit */ |
| 189 | #define G2SC 0x418 /* 8bit */ |
| 190 | #define G3SC 0x420 /* 8bit */ |
| 191 | #define G4SC 0x428 /* 8bit */ |
| 192 | #define G5SC 0x430 /* 8bit */ |
| 193 | #define G6SC 0x438 /* 8bit */ |
| 194 | |
| 195 | #define C1DRAMW 0x48c /* 16bit */ |
| 196 | #define G7SC 0x490 /* 8bit */ |
| 197 | #define G8SC 0x498 /* 8bit */ |
| 198 | |
| 199 | #define G1SRPUT 0x500 /* 256bit */ |
| 200 | #define G1SRPDT 0x520 /* 256bit */ |
| 201 | #define G2SRPUT 0x540 /* 256bit */ |
| 202 | #define G2SRPDT 0x560 /* 256bit */ |
| 203 | #define G3SRPUT 0x580 /* 256bit */ |
| 204 | #define G3SRPDT 0x5a0 /* 256bit */ |
| 205 | #define G4SRPUT 0x5c0 /* 256bit */ |
| 206 | #define G4SRPDT 0x5e0 /* 256bit */ |
| 207 | #define G5SRPUT 0x600 /* 256bit */ |
| 208 | #define G5SRPDT 0x620 /* 256bit */ |
| 209 | #define G6SRPUT 0x640 /* 256bit */ |
| 210 | #define G6SRPDT 0x660 /* 256bit */ |
| 211 | #define G7SRPUT 0x680 /* 256bit */ |
| 212 | #define G7SRPDT 0x6a0 /* 256bit */ |
| 213 | #define G8SRPUT 0x6c0 /* 256bit */ |
| 214 | #define G8SRPDT 0x6e0 /* 256bit */ |
| 215 | |
| 216 | /* Clock Controls */ |
| 217 | #define CLKCFG 0xc00 /* 32bit */ |
| 218 | #define UPMC1 0xc14 /* 16bit */ |
| 219 | #define CPCTL 0xc16 /* 16bit */ |
| 220 | #define SSKPD 0xc1c /* 16bit (scratchpad) */ |
| 221 | #define UPMC2 0xc20 /* 16bit */ |
| 222 | #define UPMC4 0xc30 /* 32bit */ |
| 223 | #define PLLMON 0xc34 /* 32bit */ |
| 224 | #define HGIPMC2 0xc38 /* 32bit */ |
| 225 | |
| 226 | /* Thermal Management Controls */ |
| 227 | #define TSC1 0xc88 /* 8bit */ |
| 228 | #define TSS1 0xc8a /* 8bit */ |
| 229 | #define TR1 0xc8b /* 8bit */ |
| 230 | #define TSTTP1 0xc8c /* 32bit */ |
| 231 | #define TCO1 0xc92 /* 8bit */ |
| 232 | #define THERM1_1 0xc94 /* 8bit */ |
| 233 | #define TCOF1 0xc96 /* 8bit */ |
| 234 | #define TIS1 0xc9a /* 16bit */ |
| 235 | #define TSTTP1_2 0xc9c /* 32bit */ |
| 236 | #define IUB 0xcd0 /* 32bit */ |
| 237 | #define TSC0_1 0xcd8 /* 8bit */ |
| 238 | #define TSS0 0xcda /* 8bit */ |
| 239 | #define TR0 0xcdb /* 8bit */ |
| 240 | #define TSTTP0_1 0xcdc /* 32bit */ |
| 241 | #define TCO0 0xce2 /* 8bit */ |
| 242 | #define THERM0_1 0xce4 /* 8bit */ |
| 243 | #define TCOF0 0xce6 /* 8bit */ |
| 244 | #define TIS0 0xcea /* 16bit */ |
| 245 | #define TSTTP0_2 0xcec /* 32bit */ |
| 246 | #define TERRCMD 0xcf0 /* 8bit */ |
| 247 | #define TSMICMD 0xcf1 /* 8bit */ |
| 248 | #define TSCICMD 0xcf2 /* 8bit */ |
| 249 | #define TINTRCMD 0xcf3 /* 8bit */ |
| 250 | #define EXTTSCS 0xcff /* 8bit */ |
| 251 | #define DFT_STRAP1 0xe08 /* 32bit */ |
| 252 | |
| 253 | /* ACPI Power Management Controls */ |
| 254 | |
| 255 | #define MIPMC3 0xbd8 /* 32bit */ |
| 256 | |
| 257 | #define C2C3TT 0xf00 /* 32bit */ |
| 258 | #define C3C4TT 0xf04 /* 32bit */ |
| 259 | |
| 260 | #define MIPMC4 0xf08 /* 16bit */ |
| 261 | #define MIPMC5 0xf0a /* 16bit */ |
| 262 | #define MIPMC6 0xf0c /* 16bit */ |
| 263 | #define MIPMC7 0xf0e /* 16bit */ |
| 264 | #define PMCFG 0xf10 /* 32bit */ |
| 265 | #define SLFRCS 0xf14 /* 32bit */ |
| 266 | #define GIPMC1 0xfb0 /* 32bit */ |
| 267 | #define FSBPMC1 0xfb8 /* 32bit */ |
| 268 | #define UPMC3 0xfc0 /* 32bit */ |
| 269 | #define ECO 0xffc /* 32bit */ |
| 270 | |
| 271 | /* |
| 272 | * EPBAR - Egress Port Root Complex Register Block |
| 273 | */ |
| 274 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 275 | #define EPPVCCAP1 0x004 /* 32bit */ |
| 276 | #define EPPVCCAP2 0x008 /* 32bit */ |
| 277 | |
| 278 | #define EPVC0RCAP 0x010 /* 32bit */ |
| 279 | #define EPVC0RCTL 0x014 /* 32bit */ |
| 280 | #define EPVC0RSTS 0x01a /* 16bit */ |
| 281 | |
| 282 | #define EPVC1RCAP 0x01c /* 32bit */ |
| 283 | #define EPVC1RCTL 0x020 /* 32bit */ |
| 284 | #define EPVC1RSTS 0x026 /* 16bit */ |
| 285 | |
| 286 | #define EPVC1MTS 0x028 /* 32bit */ |
| 287 | #define EPVC1IST 0x038 /* 64bit */ |
| 288 | |
| 289 | #define EPESD 0x044 /* 32bit */ |
| 290 | |
| 291 | #define EPLE1D 0x050 /* 32bit */ |
| 292 | #define EPLE1A 0x058 /* 64bit */ |
| 293 | #define EPLE2D 0x060 /* 32bit */ |
| 294 | #define EPLE2A 0x068 /* 64bit */ |
| 295 | |
| 296 | #define PORTARB 0x100 /* 256bit */ |
| 297 | |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 298 | /* |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 299 | * DMIBAR |
| 300 | */ |
| 301 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 302 | #define DMIVCECH 0x000 /* 32bit */ |
| 303 | #define DMIPVCCAP1 0x004 /* 32bit */ |
| 304 | #define DMIPVCCAP2 0x008 /* 32bit */ |
| 305 | |
| 306 | #define DMIPVCCCTL 0x00c /* 16bit */ |
| 307 | |
| 308 | #define DMIVC0RCAP 0x010 /* 32bit */ |
| 309 | #define DMIVC0RCTL0 0x014 /* 32bit */ |
| 310 | #define DMIVC0RSTS 0x01a /* 16bit */ |
| 311 | |
| 312 | #define DMIVC1RCAP 0x01c /* 32bit */ |
| 313 | #define DMIVC1RCTL 0x020 /* 32bit */ |
| 314 | #define DMIVC1RSTS 0x026 /* 16bit */ |
| 315 | |
| 316 | #define DMILE1D 0x050 /* 32bit */ |
| 317 | #define DMILE1A 0x058 /* 64bit */ |
| 318 | #define DMILE2D 0x060 /* 32bit */ |
| 319 | #define DMILE2A 0x068 /* 64bit */ |
| 320 | |
| 321 | #define DMILCAP 0x084 /* 32bit */ |
| 322 | #define DMILCTL 0x088 /* 16bit */ |
| 323 | #define DMILSTS 0x08a /* 16bit */ |
| 324 | |
| 325 | #define DMICTL1 0x0f0 /* 32bit */ |
| 326 | #define DMICTL2 0x0fc /* 32bit */ |
| 327 | |
| 328 | #define DMICC 0x208 /* 32bit */ |
| 329 | |
| 330 | #define DMIDRCCFG 0xeb4 /* 32bit */ |
| 331 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 332 | int i945_silicon_revision(void); |
| 333 | void i945_early_initialization(void); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 334 | void i945_late_initialization(int s3resume); |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 335 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 336 | /* debugging functions */ |
| 337 | void print_pci_devices(void); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 338 | void dump_pci_device(unsigned int dev); |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 339 | void dump_pci_devices(void); |
Angel Pons | a60b42a | 2021-03-28 14:06:55 +0200 | [diff] [blame] | 340 | void dump_spd_registers(u8 spd_map[4]); |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 341 | void sdram_dump_mchbar_registers(void); |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 342 | |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 343 | u32 decode_igd_memory_size(u32 gms); |
Arthur Heymans | f6d1477 | 2018-01-26 11:50:04 +0100 | [diff] [blame] | 344 | u32 decode_tseg_size(const u8 esmramc); |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 345 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 346 | /* Romstage mainboard callbacks */ |
| 347 | /* Optional: Override the default LPC config. */ |
| 348 | void mainboard_lpc_decode(void); |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 349 | /* Optional: mainboard specific init after console init and before raminit. */ |
| 350 | void mainboard_pre_raminit_config(int s3_resume); |
| 351 | /* Mainboard specific RCBA init. Happens after raminit. */ |
| 352 | void mainboard_late_rcba_config(void); |
| 353 | /* Optional: mainboard callback to get SPD map */ |
| 354 | void mainboard_get_spd_map(u8 spd_map[4]); |
| 355 | |
Edward O'Callaghan | a34a1da | 2014-06-01 16:09:21 +1000 | [diff] [blame] | 356 | #endif /* __ACPI__ */ |
| 357 | |
| 358 | #endif /* NORTHBRIDGE_INTEL_I945_H */ |