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Stefan Reinauer278534d2008-10-29 04:51:07 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stefan Reinauer278534d2008-10-29 04:51:07 +000014 */
15
Edward O'Callaghana34a1da2014-06-01 16:09:21 +100016#ifndef NORTHBRIDGE_INTEL_I945_H
17#define NORTHBRIDGE_INTEL_I945_H
Stefan Reinauer278534d2008-10-29 04:51:07 +000018
Stefan Reinaueraca6ec62009-10-26 17:12:21 +000019/* Northbridge BARs */
20#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
21#define DEFAULT_X60BAR 0xfed13000
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080022#ifndef __ACPI__
23#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */
24#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
25#else
Stefan Reinaueraca6ec62009-10-26 17:12:21 +000026#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
27#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080028#endif
Stefan Reinaueraca6ec62009-10-26 17:12:21 +000029#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
30
Antonello Dettoria1e1e5c2016-08-21 10:51:53 +020031#include <southbridge/intel/i82801gx/i82801gx.h>
Stefan Reinauer278534d2008-10-29 04:51:07 +000032
Stefan Reinaueraca6ec62009-10-26 17:12:21 +000033/* Everything below this line is ignored in the DSDT */
34#ifndef __ACPI__
35
Denis 'GNUtoo' Carikli7ed73942013-05-26 23:56:43 +020036/* Display defines for the interrupt 15h handler */
37#define INT15_5F35_CL_DISPLAY_DEFAULT 0
38#define INT15_5F35_CL_DISPLAY_CRT (1 << 0)
39#define INT15_5F35_CL_DISPLAY_TV (1 << 1)
40#define INT15_5F35_CL_DISPLAY_EFP (1 << 2)
41#define INT15_5F35_CL_DISPLAY_LCD (1 << 3)
42#define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4)
43#define INT15_5F35_CL_DISPLAY_TV2 (1 << 5)
44#define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6)
45#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7)
46
Stefan Reinauer278534d2008-10-29 04:51:07 +000047/* Device 0:0.0 PCI configuration space (Host Bridge) */
48
49#define EPBAR 0x40
50#define MCHBAR 0x44
51#define PCIEXBAR 0x48
52#define DMIBAR 0x4c
53#define X60BAR 0x60
54
Uwe Hermanna1637292008-11-09 10:57:26 +000055#define GGC 0x52 /* GMCH Graphics Control */
Stefan Reinauer278534d2008-10-29 04:51:07 +000056
Uwe Hermanna1637292008-11-09 10:57:26 +000057#define DEVEN 0x54 /* Device Enable */
Stefan Reinauer278534d2008-10-29 04:51:07 +000058#define DEVEN_D0F0 (1 << 0)
59#define DEVEN_D1F0 (1 << 1)
60#define DEVEN_D2F0 (1 << 3)
61#define DEVEN_D2F1 (1 << 4)
Edward O'Callaghana34a1da2014-06-01 16:09:21 +100062
Stefan Reinauer278534d2008-10-29 04:51:07 +000063#ifndef BOARD_DEVEN
Arthur Heymans70a8e342017-03-09 11:30:23 +010064#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1)
Edward O'Callaghana34a1da2014-06-01 16:09:21 +100065#endif /* BOARD_DEVEN */
Stefan Reinauer278534d2008-10-29 04:51:07 +000066
Uwe Hermanna1637292008-11-09 10:57:26 +000067#define PAM0 0x90
68#define PAM1 0x91
69#define PAM2 0x92
70#define PAM3 0x93
71#define PAM4 0x94
72#define PAM5 0x95
73#define PAM6 0x96
Stefan Reinauer278534d2008-10-29 04:51:07 +000074
Uwe Hermanna1637292008-11-09 10:57:26 +000075#define LAC 0x97 /* Legacy Access Control */
76#define TOLUD 0x9c /* Top of Low Used Memory */
77#define SMRAM 0x9d /* System Management RAM Control */
78#define ESMRAM 0x9e /* Extended System Management RAM Control */
Stefan Reinauer278534d2008-10-29 04:51:07 +000079
Uwe Hermanna1637292008-11-09 10:57:26 +000080#define TOM 0xa0
Stefan Reinauer278534d2008-10-29 04:51:07 +000081
Uwe Hermanna1637292008-11-09 10:57:26 +000082#define SKPAD 0xdc /* Scratchpad Data */
Stefan Reinauer278534d2008-10-29 04:51:07 +000083
84/* Device 0:1.0 PCI configuration space (PCI Express) */
85
Stefan Reinauer779b3e32008-11-10 15:43:37 +000086#define BCTRL1 0x3e /* 16bit */
Patrick Georgid3060ed2014-08-10 15:19:45 +020087#define PEGSTS 0x214 /* 32bit */
Stefan Reinauer278534d2008-10-29 04:51:07 +000088
89
90/* Device 0:2.0 PCI configuration space (Graphics Device) */
91
Paul Menzeld235da12014-06-03 00:15:30 +020092#define GMADR 0x18
93#define GTTADR 0x1c
Paul Menzel50684632014-06-03 00:26:03 +020094#define BSM 0x5c
Uwe Hermanna1637292008-11-09 10:57:26 +000095#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
Stefan Reinauer278534d2008-10-29 04:51:07 +000096
97
98/*
99 * MCHBAR
100 */
101
Arthur Heymans70a8e342017-03-09 11:30:23 +0100102#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
103#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
104#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
Stefan Reinauer278534d2008-10-29 04:51:07 +0000105
106/* Chipset Control Registers */
107#define FSBPMC3 0x40 /* 32bit */
108#define FSBPMC4 0x44 /* 32bit */
109#define FSBSNPCTL 0x48 /* 32bit */
110#define SLPCTL 0x90 /* 32bit */
111
112#define C0DRB0 0x100 /* 8bit */
113#define C0DRB1 0x101 /* 8bit */
114#define C0DRB2 0x102 /* 8bit */
115#define C0DRB3 0x103 /* 8bit */
116#define C0DRA0 0x108 /* 8bit */
117#define C0DRA2 0x109 /* 8bit */
118#define C0DCLKDIS 0x10c /* 8bit */
119#define C0BNKARC 0x10e /* 16bit */
120#define C0DRT0 0x110 /* 32bit */
121#define C0DRT1 0x114 /* 32bit */
122#define C0DRT2 0x118 /* 32bit */
123#define C0DRT3 0x11c /* 32bit */
124#define C0DRC0 0x120 /* 32bit */
125#define C0DRC1 0x124 /* 32bit */
126#define C0DRC2 0x128 /* 32bit */
127#define C0AIT 0x130 /* 64bit */
128#define C0DCCFT 0x138 /* 64bit */
129#define C0GTEW 0x140 /* 32bit */
130#define C0GTC 0x144 /* 32bit */
131#define C0DTPEW 0x148 /* 64bit */
132#define C0DTAEW 0x150 /* 64bit */
133#define C0DTC 0x158 /* 32bit */
134#define C0DMC 0x164 /* 32bit */
135#define C0ODT 0x168 /* 64bit */
136
137#define C1DRB0 0x180 /* 8bit */
138#define C1DRB1 0x181 /* 8bit */
139#define C1DRB2 0x182 /* 8bit */
140#define C1DRB3 0x183 /* 8bit */
141#define C1DRA0 0x188 /* 8bit */
Uwe Hermanna1637292008-11-09 10:57:26 +0000142#define C1DRA2 0x189 /* 8bit */
Stefan Reinauer278534d2008-10-29 04:51:07 +0000143#define C1DCLKDIS 0x18c /* 8bit */
144#define C1BNKARC 0x18e /* 16bit */
145#define C1DRT0 0x190 /* 32bit */
146#define C1DRT1 0x194 /* 32bit */
147#define C1DRT2 0x198 /* 32bit */
148#define C1DRT3 0x19c /* 32bit */
149#define C1DRC0 0x1a0 /* 32bit */
150#define C1DRC1 0x1a4 /* 32bit */
151#define C1DRC2 0x1a8 /* 32bit */
152#define C1AIT 0x1b0 /* 64bit */
153#define C1DCCFT 0x1b8 /* 64bit */
154#define C1GTEW 0x1c0 /* 32bit */
155#define C1GTC 0x1c4 /* 32bit */
156#define C1DTPEW 0x1c8 /* 64bit */
157#define C1DTAEW 0x1d0 /* 64bit */
158#define C1DTC 0x1d8 /* 32bit */
159#define C1DMC 0x1e4 /* 32bit */
160#define C1ODT 0x1e8 /* 64bit */
161
162#define DCC 0x200 /* 32bit */
163#define CCCFT 0x208 /* 64bit */
164#define WCC 0x218 /* 32bit */
165#define MMARB0 0x220 /* 32bit */
166#define MMARB1 0x224 /* 32bit */
167#define SBTEST 0x230 /* 32bit */
168#define SBOCC 0x238 /* 32bit */
169#define ODTC 0x284 /* 32bit */
170#define SMVREFC 0x2a0 /* 32bit */
171#define DRTST 0x2a8 /* 32bit */
172#define REPC 0x2e0 /* 32bit */
173#define DQSMT 0x2f4 /* 16bit */
174#define RCVENMT 0x2f8 /* 32bit */
175
Uwe Hermanna1637292008-11-09 10:57:26 +0000176#define C0R0B00DQST 0x300 /* 64bit */
Stefan Reinauer278534d2008-10-29 04:51:07 +0000177
178#define C0WL0REOST 0x340 /* 8bit */
179#define C0WL1REOST 0x341 /* 8bit */
180#define C0WL2REOST 0x342 /* 8bit */
181#define C0WL3REOST 0x343 /* 8bit */
182#define WDLLBYPMODE 0x360 /* 16bit */
183#define C0WDLLCMC 0x36c /* 32bit */
184#define C0HCTC 0x37c /* 8bit */
185
Uwe Hermanna1637292008-11-09 10:57:26 +0000186#define C1R0B00DQST 0x380 /* 64bit */
Stefan Reinauer278534d2008-10-29 04:51:07 +0000187
188#define C1WL0REOST 0x3c0 /* 8bit */
189#define C1WL1REOST 0x3c1 /* 8bit */
190#define C1WL2REOST 0x3c2 /* 8bit */
191#define C1WL3REOST 0x3c3 /* 8bit */
192#define C1WDLLCMC 0x3ec /* 32bit */
193#define C1HCTC 0x3fc /* 8bit */
194
195#define GBRCOMPCTL 0x400 /* 32bit */
196
197#define SMSRCTL 0x408 /* XXX who knows */
198#define C0DRAMW 0x40c /* 16bit */
199#define G1SC 0x410 /* 8bit */
200#define G2SC 0x418 /* 8bit */
201#define G3SC 0x420 /* 8bit */
202#define G4SC 0x428 /* 8bit */
203#define G5SC 0x430 /* 8bit */
204#define G6SC 0x438 /* 8bit */
205
206#define C1DRAMW 0x48c /* 16bit */
207#define G7SC 0x490 /* 8bit */
208#define G8SC 0x498 /* 8bit */
209
210#define G1SRPUT 0x500 /* 256bit */
211#define G1SRPDT 0x520 /* 256bit */
212#define G2SRPUT 0x540 /* 256bit */
213#define G2SRPDT 0x560 /* 256bit */
214#define G3SRPUT 0x580 /* 256bit */
215#define G3SRPDT 0x5a0 /* 256bit */
216#define G4SRPUT 0x5c0 /* 256bit */
217#define G4SRPDT 0x5e0 /* 256bit */
218#define G5SRPUT 0x600 /* 256bit */
219#define G5SRPDT 0x620 /* 256bit */
220#define G6SRPUT 0x640 /* 256bit */
221#define G6SRPDT 0x660 /* 256bit */
222#define G7SRPUT 0x680 /* 256bit */
223#define G7SRPDT 0x6a0 /* 256bit */
224#define G8SRPUT 0x6c0 /* 256bit */
225#define G8SRPDT 0x6e0 /* 256bit */
226
227/* Clock Controls */
228#define CLKCFG 0xc00 /* 32bit */
229#define UPMC1 0xc14 /* 16bit */
230#define CPCTL 0xc16 /* 16bit */
231#define SSKPD 0xc1c /* 16bit (scratchpad) */
232#define UPMC2 0xc20 /* 16bit */
233#define UPMC4 0xc30 /* 32bit */
234#define PLLMON 0xc34 /* 32bit */
235#define HGIPMC2 0xc38 /* 32bit */
236
237/* Thermal Management Controls */
238#define TSC1 0xc88 /* 8bit */
239#define TSS1 0xc8a /* 8bit */
240#define TR1 0xc8b /* 8bit */
241#define TSTTP1 0xc8c /* 32bit */
242#define TCO1 0xc92 /* 8bit */
243#define THERM1_1 0xc94 /* 8bit */
244#define TCOF1 0xc96 /* 8bit */
245#define TIS1 0xc9a /* 16bit */
246#define TSTTP1_2 0xc9c /* 32bit */
247#define IUB 0xcd0 /* 32bit */
248#define TSC0_1 0xcd8 /* 8bit */
249#define TSS0 0xcda /* 8bit */
250#define TR0 0xcdb /* 8bit */
251#define TSTTP0_1 0xcdc /* 32bit */
252#define TCO0 0xce2 /* 8bit */
253#define THERM0_1 0xce4 /* 8bit */
254#define TCOF0 0xce6 /* 8bit */
255#define TIS0 0xcea /* 16bit */
256#define TSTTP0_2 0xcec /* 32bit */
257#define TERRCMD 0xcf0 /* 8bit */
258#define TSMICMD 0xcf1 /* 8bit */
259#define TSCICMD 0xcf2 /* 8bit */
260#define TINTRCMD 0xcf3 /* 8bit */
261#define EXTTSCS 0xcff /* 8bit */
262#define DFT_STRAP1 0xe08 /* 32bit */
263
264/* ACPI Power Management Controls */
265
266#define MIPMC3 0xbd8 /* 32bit */
267
268#define C2C3TT 0xf00 /* 32bit */
269#define C3C4TT 0xf04 /* 32bit */
270
271#define MIPMC4 0xf08 /* 16bit */
272#define MIPMC5 0xf0a /* 16bit */
273#define MIPMC6 0xf0c /* 16bit */
274#define MIPMC7 0xf0e /* 16bit */
275#define PMCFG 0xf10 /* 32bit */
276#define SLFRCS 0xf14 /* 32bit */
277#define GIPMC1 0xfb0 /* 32bit */
278#define FSBPMC1 0xfb8 /* 32bit */
279#define UPMC3 0xfc0 /* 32bit */
280#define ECO 0xffc /* 32bit */
281
282/*
283 * EPBAR - Egress Port Root Complex Register Block
284 */
285
Arthur Heymans70a8e342017-03-09 11:30:23 +0100286#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
287#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
288#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
Stefan Reinauer278534d2008-10-29 04:51:07 +0000289
290#define EPPVCCAP1 0x004 /* 32bit */
291#define EPPVCCAP2 0x008 /* 32bit */
292
293#define EPVC0RCAP 0x010 /* 32bit */
294#define EPVC0RCTL 0x014 /* 32bit */
295#define EPVC0RSTS 0x01a /* 16bit */
296
297#define EPVC1RCAP 0x01c /* 32bit */
298#define EPVC1RCTL 0x020 /* 32bit */
299#define EPVC1RSTS 0x026 /* 16bit */
300
301#define EPVC1MTS 0x028 /* 32bit */
302#define EPVC1IST 0x038 /* 64bit */
303
304#define EPESD 0x044 /* 32bit */
305
306#define EPLE1D 0x050 /* 32bit */
307#define EPLE1A 0x058 /* 64bit */
308#define EPLE2D 0x060 /* 32bit */
309#define EPLE2A 0x068 /* 64bit */
310
311#define PORTARB 0x100 /* 256bit */
312
Stefan Reinauer109ab312009-08-12 16:08:05 +0000313/*
Stefan Reinauer278534d2008-10-29 04:51:07 +0000314 * DMIBAR
315 */
316
Arthur Heymans70a8e342017-03-09 11:30:23 +0100317#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
318#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
319#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
Stefan Reinauer278534d2008-10-29 04:51:07 +0000320
321#define DMIVCECH 0x000 /* 32bit */
322#define DMIPVCCAP1 0x004 /* 32bit */
323#define DMIPVCCAP2 0x008 /* 32bit */
324
325#define DMIPVCCCTL 0x00c /* 16bit */
326
327#define DMIVC0RCAP 0x010 /* 32bit */
328#define DMIVC0RCTL0 0x014 /* 32bit */
329#define DMIVC0RSTS 0x01a /* 16bit */
330
331#define DMIVC1RCAP 0x01c /* 32bit */
332#define DMIVC1RCTL 0x020 /* 32bit */
333#define DMIVC1RSTS 0x026 /* 16bit */
334
335#define DMILE1D 0x050 /* 32bit */
336#define DMILE1A 0x058 /* 64bit */
337#define DMILE2D 0x060 /* 32bit */
338#define DMILE2A 0x068 /* 64bit */
339
340#define DMILCAP 0x084 /* 32bit */
341#define DMILCTL 0x088 /* 16bit */
342#define DMILSTS 0x08a /* 16bit */
343
344#define DMICTL1 0x0f0 /* 32bit */
345#define DMICTL2 0x0fc /* 32bit */
346
347#define DMICC 0x208 /* 32bit */
348
349#define DMIDRCCFG 0xeb4 /* 32bit */
350
Stefan Reinauerbf264e92010-05-14 19:09:20 +0000351static inline void barrier(void) { asm("" ::: "memory"); }
352
Patrick Georgid0835952010-10-05 09:07:10 +0000353int i945_silicon_revision(void);
354void i945_early_initialization(void);
Vladimir Serbinenko55601882014-10-15 20:17:51 +0200355void i945_late_initialization(int s3resume);
Patrick Georgid0835952010-10-05 09:07:10 +0000356
Patrick Georgid0835952010-10-05 09:07:10 +0000357/* provided by mainboard code */
358void setup_ich7_gpios(void);
359
360/* debugging functions */
361void print_pci_devices(void);
Arthur Heymans70a8e342017-03-09 11:30:23 +0100362void dump_pci_device(unsigned int dev);
Patrick Georgid0835952010-10-05 09:07:10 +0000363void dump_pci_devices(void);
364void dump_spd_registers(void);
Arthur Heymans70a8e342017-03-09 11:30:23 +0100365void dump_mem(unsigned int start, unsigned int end);
Patrick Georgid0835952010-10-05 09:07:10 +0000366
Arthur Heymans874a8f92016-05-19 16:06:09 +0200367u32 decode_igd_memory_size(u32 gms);
368
Edward O'Callaghana34a1da2014-06-01 16:09:21 +1000369#endif /* __ACPI__ */
370
371#endif /* NORTHBRIDGE_INTEL_I945_H */