Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
Felix Held | 95f1bb8 | 2021-05-07 18:46:36 +0200 | [diff] [blame] | 4 | #include <amdblocks/alib.h> |
Arthur Heymans | ce17972 | 2023-06-07 15:27:18 +0200 | [diff] [blame] | 5 | #include <amdblocks/data_fabric.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 6 | #include <amdblocks/ioapic.h> |
Felix Held | 43662b5 | 2023-07-18 20:36:34 +0200 | [diff] [blame] | 7 | #include <amdblocks/root_complex.h> |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 11 | #include <stdint.h> |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 12 | #include <soc/iomap.h> |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 13 | #include "chip.h" |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 14 | |
Felix Held | ef51157 | 2021-05-07 19:02:45 +0200 | [diff] [blame] | 15 | #define DPTC_TOTAL_UPDATE_PARAMS 4 |
| 16 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 17 | struct dptc_input { |
| 18 | uint16_t size; |
Felix Held | f061017 | 2021-05-07 19:21:08 +0200 | [diff] [blame] | 19 | struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 20 | } __packed; |
| 21 | |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 22 | #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ |
Felix Held | 3acafa2 | 2021-05-07 19:17:51 +0200 | [diff] [blame] | 23 | { \ |
| 24 | .size = sizeof(struct dptc_input), \ |
| 25 | .params = { \ |
| 26 | { \ |
| 27 | .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ |
| 28 | .value = _thermctllmit, \ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 29 | }, \ |
Felix Held | 3acafa2 | 2021-05-07 19:17:51 +0200 | [diff] [blame] | 30 | { \ |
| 31 | .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ |
| 32 | .value = _sustained, \ |
| 33 | }, \ |
| 34 | { \ |
| 35 | .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ |
| 36 | .value = _fast, \ |
| 37 | }, \ |
| 38 | { \ |
| 39 | .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ |
| 40 | .value = _slow, \ |
| 41 | }, \ |
| 42 | }, \ |
| 43 | } |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 44 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 45 | static void acipgen_dptci(void) |
| 46 | { |
Felix Held | 507fc03 | 2020-12-05 01:55:27 +0100 | [diff] [blame] | 47 | const struct soc_amd_picasso_config *config = config_of_soc(); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 48 | |
Tim Van Patten | 54ce4aa | 2022-09-13 14:37:32 -0600 | [diff] [blame] | 49 | /* Normal mode DPTC values. */ |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 50 | struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, |
| 51 | config->sustained_power_limit_mW, |
| 52 | config->fast_ppt_limit_mW, |
| 53 | config->slow_ppt_limit_mW); |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 54 | acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); |
| 55 | |
| 56 | /* Tablet Mode */ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 57 | struct dptc_input tablet_mode_input = DPTC_INPUTS( |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 58 | config->thermctl_limit_tablet_mode_degreeC, |
| 59 | config->sustained_power_limit_tablet_mode_mW, |
| 60 | config->fast_ppt_limit_tablet_mode_mW, |
| 61 | config->slow_ppt_limit_tablet_mode_mW); |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 62 | acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input, |
| 63 | sizeof(tablet_mode_input)); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 64 | } |
| 65 | |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 66 | static void root_complex_fill_ssdt(const struct device *device) |
| 67 | { |
Tim Van Patten | 54ce4aa | 2022-09-13 14:37:32 -0600 | [diff] [blame] | 68 | if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) |
| 69 | acipgen_dptci(); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 70 | } |
| 71 | |
Felix Held | ff092d4 | 2021-02-17 00:04:59 +0100 | [diff] [blame] | 72 | static const char *gnb_acpi_name(const struct device *dev) |
| 73 | { |
| 74 | return "GNB"; |
| 75 | } |
| 76 | |
Arthur Heymans | 826955d | 2022-09-20 17:26:30 +0200 | [diff] [blame] | 77 | struct device_operations picasso_root_complex_operations = { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 78 | /* The root complex has no PCI BARs implemented, so there's no need to call |
| 79 | pci_dev_read_resources for it */ |
| 80 | .read_resources = noop_read_resources, |
Felix Held | 9541d17 | 2021-01-05 00:56:10 +0100 | [diff] [blame] | 81 | .set_resources = noop_set_resources, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 82 | .enable_resources = pci_dev_enable_resources, |
Felix Held | ff092d4 | 2021-02-17 00:04:59 +0100 | [diff] [blame] | 83 | .acpi_name = gnb_acpi_name, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 84 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
| 85 | }; |
Felix Held | 43662b5 | 2023-07-18 20:36:34 +0200 | [diff] [blame] | 86 | |
| 87 | uint32_t get_iohc_misc_smn_base(struct device *domain) |
| 88 | { |
Felix Held | 69ffebf | 2023-07-24 21:31:44 +0200 | [diff] [blame] | 89 | return SMN_IOHC_MISC_BASE_13B1; |
Felix Held | 43662b5 | 2023-07-18 20:36:34 +0200 | [diff] [blame] | 90 | } |
| 91 | |
| 92 | static const struct non_pci_mmio_reg non_pci_mmio[] = { |
| 93 | { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 94 | { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 95 | /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we |
| 96 | tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB |
| 97 | resource. */ |
| 98 | { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, |
| 99 | { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 100 | { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 101 | { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 102 | { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 103 | }; |
| 104 | |
| 105 | const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) |
| 106 | { |
| 107 | *count = ARRAY_SIZE(non_pci_mmio); |
| 108 | return non_pci_mmio; |
| 109 | } |
Felix Held | b0ab545 | 2023-08-11 22:24:00 +0200 | [diff] [blame] | 110 | |
| 111 | signed int get_iohc_fabric_id(struct device *domain) |
| 112 | { |
| 113 | switch (domain->path.domain.domain) { |
| 114 | case 0: |
| 115 | return IOMS0_FABRIC_ID; |
| 116 | default: |
| 117 | return -1; |
| 118 | } |
| 119 | } |