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Angel Ponsfabfe9d2020-04-05 15:47:07 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aamir Bohradd7acaa2020-03-25 11:36:22 +05302
Aamir Bohradd7acaa2020-03-25 11:36:22 +05303#include <bootstate.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -07004#include <commonlib/console/post_codes.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +05305#include <console/console.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +05306#include <cpu/x86/smm.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -07007#include <device/mmio.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +05308#include <device/pci.h>
9#include <intelblocks/lpc_lib.h>
10#include <intelblocks/pcr.h>
Subrata Banik0359d9d2020-09-28 18:43:47 +053011#include <intelblocks/pmclib.h>
Tim Wawrzynczak9ed17512021-08-26 09:07:44 -060012#include <intelblocks/systemagent.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +053013#include <intelblocks/tco.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +053014#include <soc/p2sb.h>
15#include <soc/pci_devs.h>
16#include <soc/pcr_ids.h>
17#include <soc/pm.h>
18#include <soc/smbus.h>
19#include <soc/soc_chip.h>
20#include <soc/systemagent.h>
Ricardo Quesada470ca5712021-07-16 16:39:28 -070021#include <spi-generic.h>
Aamir Bohradd7acaa2020-03-25 11:36:22 +053022
23#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
24#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
25#define CAM_CLK_EN (1 << 1)
26#define MIPI_CLK (1 << 0)
27#define HDPLL_CLK (0 << 0)
28
29static void pch_enable_isclk(void)
30{
31 pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
32 pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
33}
34
35static void pch_handle_sideband(config_t *config)
36{
37 if (config->pch_isclk)
38 pch_enable_isclk();
39}
40
41static void pch_finalize(void)
42{
Krishna Prasad Bhat830306c2020-12-30 14:01:40 +053043 uint32_t reg32;
44 uint8_t *pmcbase;
Michael Niewöhnerd2fadda2021-09-27 19:26:20 +020045 config_t *config = config_of_soc();
Aamir Bohradd7acaa2020-03-25 11:36:22 +053046
47 /* TCO Lock down */
48 tco_lockdown();
49
50 /* TODO: Add Thermal Configuration */
51
Krishna Prasad Bhat830306c2020-12-30 14:01:40 +053052 pmcbase = pmc_mmio_regs();
53 if (config->s0ix_enable) {
54 /*
55 * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
56 * before entering s0ix.
57 */
58 reg32 = read32(pmcbase + CPPMVRIC3);
59 reg32 &= ~USBSUSPGQDIS;
60 write32(pmcbase + CPPMVRIC3, reg32);
Jamie Chen5b589022022-03-15 16:16:30 +080061
62 if (config->cnvi_reduce_s0ix_pwr_usage) {
63 setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);
64 setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0));
65 }
Krishna Prasad Bhat830306c2020-12-30 14:01:40 +053066 }
67
Aamir Bohradd7acaa2020-03-25 11:36:22 +053068 pch_handle_sideband(config);
69
70 pmc_clear_pmcon_sts();
71}
72
73static void soc_finalize(void *unused)
74{
75 printk(BIOS_DEBUG, "Finalizing chipset.\n");
76
77 pch_finalize();
Kyösti Mälkkib6585482020-06-01 15:11:14 +030078 apm_control(APM_CNT_FINALIZE);
Aamir Bohradd7acaa2020-03-25 11:36:22 +053079
80 /* Indicate finalize step with post code */
lilacious40cb3fe2023-06-21 23:24:14 +020081 post_code(POSTCODE_OS_BOOT);
Aamir Bohradd7acaa2020-03-25 11:36:22 +053082}
83
84BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
85BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);