Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | #include <bootstate.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 4 | #include <commonlib/console/post_codes.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 6 | #include <cpu/x86/smm.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 7 | #include <device/mmio.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 8 | #include <device/pci.h> |
| 9 | #include <intelblocks/lpc_lib.h> |
| 10 | #include <intelblocks/pcr.h> |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 11 | #include <intelblocks/pmclib.h> |
Tim Wawrzynczak | 9ed1751 | 2021-08-26 09:07:44 -0600 | [diff] [blame] | 12 | #include <intelblocks/systemagent.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 13 | #include <intelblocks/tco.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 14 | #include <soc/p2sb.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pcr_ids.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/smbus.h> |
| 19 | #include <soc/soc_chip.h> |
| 20 | #include <soc/systemagent.h> |
Ricardo Quesada | 470ca571 | 2021-07-16 16:39:28 -0700 | [diff] [blame] | 21 | #include <spi-generic.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 22 | |
| 23 | #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ |
| 24 | #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ |
| 25 | #define CAM_CLK_EN (1 << 1) |
| 26 | #define MIPI_CLK (1 << 0) |
| 27 | #define HDPLL_CLK (0 << 0) |
| 28 | |
| 29 | static void pch_enable_isclk(void) |
| 30 | { |
| 31 | pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); |
| 32 | pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); |
| 33 | } |
| 34 | |
| 35 | static void pch_handle_sideband(config_t *config) |
| 36 | { |
| 37 | if (config->pch_isclk) |
| 38 | pch_enable_isclk(); |
| 39 | } |
| 40 | |
| 41 | static void pch_finalize(void) |
| 42 | { |
Krishna Prasad Bhat | 830306c | 2020-12-30 14:01:40 +0530 | [diff] [blame] | 43 | uint32_t reg32; |
| 44 | uint8_t *pmcbase; |
Michael Niewöhner | d2fadda | 2021-09-27 19:26:20 +0200 | [diff] [blame] | 45 | config_t *config = config_of_soc(); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 46 | |
| 47 | /* TCO Lock down */ |
| 48 | tco_lockdown(); |
| 49 | |
| 50 | /* TODO: Add Thermal Configuration */ |
| 51 | |
Krishna Prasad Bhat | 830306c | 2020-12-30 14:01:40 +0530 | [diff] [blame] | 52 | pmcbase = pmc_mmio_regs(); |
| 53 | if (config->s0ix_enable) { |
| 54 | /* |
| 55 | * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated |
| 56 | * before entering s0ix. |
| 57 | */ |
| 58 | reg32 = read32(pmcbase + CPPMVRIC3); |
| 59 | reg32 &= ~USBSUSPGQDIS; |
| 60 | write32(pmcbase + CPPMVRIC3, reg32); |
Jamie Chen | 5b58902 | 2022-03-15 16:16:30 +0800 | [diff] [blame] | 61 | |
| 62 | if (config->cnvi_reduce_s0ix_pwr_usage) { |
| 63 | setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS); |
| 64 | setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0)); |
| 65 | } |
Krishna Prasad Bhat | 830306c | 2020-12-30 14:01:40 +0530 | [diff] [blame] | 66 | } |
| 67 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 68 | pch_handle_sideband(config); |
| 69 | |
| 70 | pmc_clear_pmcon_sts(); |
| 71 | } |
| 72 | |
| 73 | static void soc_finalize(void *unused) |
| 74 | { |
| 75 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 76 | |
| 77 | pch_finalize(); |
Kyösti Mälkki | b658548 | 2020-06-01 15:11:14 +0300 | [diff] [blame] | 78 | apm_control(APM_CNT_FINALIZE); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 79 | |
| 80 | /* Indicate finalize step with post code */ |
| 81 | post_code(POST_OS_BOOT); |
| 82 | } |
| 83 | |
| 84 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 85 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |