Patrick Georgi | 7051707 | 2020-05-10 18:47:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #ifndef PEI_DATA_H |
| 4 | #define PEI_DATA_H |
| 5 | |
Elyes HAOUAS | c4e4193 | 2018-11-01 11:29:50 +0100 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 8 | typedef void (*tx_byte_func)(unsigned char byte); |
Stefan Reinauer | 190688c | 2013-08-13 11:18:42 -0700 | [diff] [blame] | 9 | #define PEI_VERSION 15 |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 10 | |
Angel Pons | 9a094c4 | 2021-02-11 14:24:03 +0100 | [diff] [blame] | 11 | #define SPD_LEN 256 |
| 12 | |
Angel Pons | d0f971f | 2021-03-12 14:20:05 +0100 | [diff] [blame] | 13 | #define PEI_USB_OC_PIN_SKIP 8 |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 14 | |
Angel Pons | d0f971f | 2021-03-12 14:20:05 +0100 | [diff] [blame] | 15 | enum pei_usb2_port_location { |
| 16 | PEI_USB_PORT_BACK_PANEL = 0, |
| 17 | PEI_USB_PORT_FRONT_PANEL, |
| 18 | PEI_USB_PORT_DOCK, |
| 19 | PEI_USB_PORT_MINI_PCIE, |
| 20 | PEI_USB_PORT_FLEX, |
| 21 | PEI_USB_PORT_INTERNAL, |
| 22 | PEI_USB_PORT_SKIP |
Duncan Laurie | bcfcfa4 | 2013-06-03 10:41:12 -0700 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | /* Usb Port Length: |
| 26 | * [16:4] = length in inches in octal format |
| 27 | * [3:0] = decimal point |
| 28 | */ |
Angel Pons | d0f971f | 2021-03-12 14:20:05 +0100 | [diff] [blame] | 29 | struct pei_usb2_port_setting { |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 30 | uint16_t length; |
| 31 | uint8_t enable; |
| 32 | uint8_t over_current_pin; |
Duncan Laurie | bcfcfa4 | 2013-06-03 10:41:12 -0700 | [diff] [blame] | 33 | uint8_t location; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 34 | } __packed; |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 35 | |
Angel Pons | d0f971f | 2021-03-12 14:20:05 +0100 | [diff] [blame] | 36 | struct pei_usb3_port_setting { |
Aaron Durbin | b1c25e7 | 2013-05-23 15:57:46 -0500 | [diff] [blame] | 37 | uint8_t enable; |
| 38 | uint8_t over_current_pin; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 39 | } __packed; |
Aaron Durbin | 8256a9b | 2012-11-29 17:18:53 -0600 | [diff] [blame] | 40 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 41 | struct pei_data |
| 42 | { |
| 43 | uint32_t pei_version; |
| 44 | uint32_t mchbar; |
| 45 | uint32_t dmibar; |
| 46 | uint32_t epbar; |
| 47 | uint32_t pciexbar; |
| 48 | uint16_t smbusbar; |
Angel Pons | e8abb5a | 2020-04-15 15:01:53 +0200 | [diff] [blame] | 49 | /* Unused by HSW MRC, but changes to the memory layout of this struct break the ABI */ |
| 50 | uint32_t _unused_wdbbar; |
| 51 | uint32_t _unused_wdbsize; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | uint32_t hpet_address; |
| 53 | uint32_t rcba; |
| 54 | uint32_t pmbase; |
| 55 | uint32_t gpiobase; |
Aaron Durbin | 8256a9b | 2012-11-29 17:18:53 -0600 | [diff] [blame] | 56 | uint32_t temp_mmio_base; |
Angel Pons | 6ba3a07 | 2020-04-24 17:42:19 +0200 | [diff] [blame] | 57 | /* System type: 0 => Mobile, 1 => Desktop/Server, 5 => ULT, Others => Reserved */ |
| 58 | uint32_t system_type; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 59 | uint32_t tseg_size; |
| 60 | uint8_t spd_addresses[4]; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | int boot_mode; |
| 62 | int ec_present; |
Stefan Reinauer | 1cc3416 | 2013-06-27 15:59:18 -0700 | [diff] [blame] | 63 | int gbe_enable; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | // 0 = leave channel enabled |
| 65 | // 1 = disable dimm 0 on channel |
| 66 | // 2 = disable dimm 1 on channel |
| 67 | // 3 = disable dimm 0+1 on channel |
| 68 | int dimm_channel0_disabled; |
| 69 | int dimm_channel1_disabled; |
Duncan Laurie | bcfcfa4 | 2013-06-03 10:41:12 -0700 | [diff] [blame] | 70 | /* Enable 2x Refresh Mode */ |
| 71 | int ddr_refresh_2x; |
Stefan Reinauer | 190688c | 2013-08-13 11:18:42 -0700 | [diff] [blame] | 72 | int dq_pins_interleaved; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | /* Data read from flash and passed into MRC */ |
| 74 | unsigned char *mrc_input; |
| 75 | unsigned int mrc_input_len; |
| 76 | /* Data from MRC that should be saved to flash */ |
| 77 | unsigned char *mrc_output; |
| 78 | unsigned int mrc_output_len; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 79 | /* Max frequency to run DDR3 at. Can be one of four values: 800, 1067, 1333, 1600 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 80 | uint32_t max_ddr3_freq; |
Duncan Laurie | 289bac6 | 2013-07-30 15:41:42 -0700 | [diff] [blame] | 81 | /* Route all USB ports to XHCI controller in resume path */ |
| 82 | int usb_xhci_on_resume; |
Angel Pons | d0f971f | 2021-03-12 14:20:05 +0100 | [diff] [blame] | 83 | struct pei_usb2_port_setting usb2_ports[16]; |
| 84 | struct pei_usb3_port_setting usb3_ports[16]; |
Angel Pons | 9a094c4 | 2021-02-11 14:24:03 +0100 | [diff] [blame] | 85 | uint8_t spd_data[4][SPD_LEN]; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | tx_byte_func tx_byte; |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 87 | } __packed; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | |
| 89 | #endif |