haswell: add option to change DqPinsInterleaved
Some mainboards will need to have this set.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
Reviewed-on: https://gerrit.chromium.org/gerrit/65722
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index f9d6e8b..f92c0a6 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,7 +31,7 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 14
+#define PEI_VERSION 15
#define MAX_USB2_PORTS 16
#define MAX_USB3_PORTS 16
@@ -92,6 +92,7 @@
int dimm_channel1_disabled;
/* Enable 2x Refresh Mode */
int ddr_refresh_2x;
+ int dq_pins_interleaved;
/* Data read from flash and passed into MRC */
unsigned char *mrc_input;
unsigned int mrc_input_len;