Patrick Georgi | d1e50f9 | 2020-03-04 15:00:05 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Early initialization code for riscv |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
Jonathan Neuschäfer | a5c49b8 | 2018-02-16 13:36:46 +0100 | [diff] [blame] | 6 | #include <arch/encoding.h> |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 7 | #include <arch/exception.h> |
Jonathan Neuschäfer | b6648cd | 2016-08-22 19:37:15 +0200 | [diff] [blame] | 8 | #include <console/console.h> |
Jonathan Neuschäfer | b6648cd | 2016-08-22 19:37:15 +0200 | [diff] [blame] | 9 | #include <vm.h> |
Xiang Wang | 22e0c56 | 2018-08-15 16:27:05 +0800 | [diff] [blame] | 10 | #include <mcall.h> |
| 11 | #include <sbi.h> |
Felix Held | dd9edef | 2021-09-16 21:51:06 +0200 | [diff] [blame] | 12 | #include <types.h> |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 13 | |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 14 | static const char *const exception_names[] = { |
| 15 | "Instruction address misaligned", |
| 16 | "Instruction access fault", |
| 17 | "Illegal instruction", |
| 18 | "Breakpoint", |
| 19 | "Load address misaligned", |
| 20 | "Load access fault", |
| 21 | "Store address misaligned", |
| 22 | "Store access fault", |
| 23 | "Environment call from U-mode", |
| 24 | "Environment call from S-mode", |
Jonathan Neuschäfer | a5c49b8 | 2018-02-16 13:36:46 +0100 | [diff] [blame] | 25 | "Reserved (10)", |
| 26 | "Environment call from M-mode", |
| 27 | "Instruction page fault", |
| 28 | "Load page fault", |
| 29 | "Reserved (14)", |
| 30 | "Store page fault", |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | static const char *mstatus_to_previous_mode(uintptr_t ms) |
| 34 | { |
| 35 | switch (ms & MSTATUS_MPP) { |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 36 | case 0x00000000: |
| 37 | return "user"; |
| 38 | case 0x00000800: |
| 39 | return "supervisor"; |
| 40 | case 0x00001000: |
| 41 | return "hypervisor"; |
| 42 | case 0x00001800: |
| 43 | return "machine"; |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | return "unknown"; |
| 47 | } |
| 48 | |
Maximilian Brune | 5d0fa0d | 2024-03-07 22:56:27 +0100 | [diff] [blame] | 49 | static void print_trap_information(const struct trapframe *tf) |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 50 | { |
| 51 | const char *previous_mode; |
| 52 | bool mprv = !!(tf->status & MSTATUS_MPRV); |
Philipp Hug | 909be6a | 2018-10-26 13:00:26 +0200 | [diff] [blame] | 53 | int hart_id = read_csr(mhartid); |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 54 | |
| 55 | /* Leave some space around the trap message */ |
| 56 | printk(BIOS_DEBUG, "\n"); |
| 57 | |
| 58 | if (tf->cause < ARRAY_SIZE(exception_names)) |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 59 | printk(BIOS_DEBUG, "Exception: %s\n", exception_names[tf->cause]); |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 60 | else |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "Trap: Unknown cause %p\n", (void *)tf->cause); |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 62 | |
| 63 | previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); |
Philipp Hug | 909be6a | 2018-10-26 13:00:26 +0200 | [diff] [blame] | 64 | printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "Previous mode: %s%s\n", previous_mode, mprv ? " (MPRV)" : ""); |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 66 | printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); |
| 67 | printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); |
Elyes Haouas | 2ba796e | 2022-11-18 15:21:37 +0100 | [diff] [blame] | 68 | printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]); |
| 69 | printk(BIOS_DEBUG, "Stored sp: %p\n", (void *)tf->gpr[2]); |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 70 | } |
| 71 | |
Maximilian Brune | 5d0fa0d | 2024-03-07 22:56:27 +0100 | [diff] [blame] | 72 | static void interrupt_handler(struct trapframe *tf) |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 73 | { |
| 74 | uint64_t cause = tf->cause & ~0x8000000000000000ULL; |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 75 | |
| 76 | switch (cause) { |
| 77 | case IRQ_M_TIMER: |
Philipp Hug | 1ed082b | 2018-10-29 21:32:51 +0100 | [diff] [blame] | 78 | /* |
| 79 | * Set interrupt pending for supervisor mode and disable timer |
| 80 | * interrupt in machine mode. |
| 81 | * To receive another timer interrupt just set timecmp and |
| 82 | * enable machine mode timer interrupt again. |
| 83 | */ |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 84 | |
Philipp Hug | 1ed082b | 2018-10-29 21:32:51 +0100 | [diff] [blame] | 85 | clear_csr(mie, MIP_MTIP); |
| 86 | set_csr(mip, MIP_STIP); |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 87 | |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 88 | break; |
Xiang Wang | 22e0c56 | 2018-08-15 16:27:05 +0800 | [diff] [blame] | 89 | case IRQ_M_SOFT: |
| 90 | if (HLS()->ipi_pending & IPI_SOFT) { |
| 91 | set_csr(mip, MIP_SSIP); |
| 92 | } else if (HLS()->ipi_pending & IPI_FENCE_I) { |
| 93 | asm volatile("fence.i"); |
| 94 | } else if (HLS()->ipi_pending & IPI_SFENCE_VMA) { |
| 95 | asm volatile("sfence.vma"); |
| 96 | } else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) { |
| 97 | asm volatile("sfence.vma"); |
| 98 | } else if (HLS()->ipi_pending & IPI_SHUTDOWN) { |
| 99 | while (HLS()->ipi_pending & IPI_SHUTDOWN) |
| 100 | asm volatile("wfi"); |
| 101 | } |
| 102 | break; |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 103 | default: |
| 104 | printk(BIOS_EMERG, "======================================\n"); |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 105 | printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n", cause); |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 106 | printk(BIOS_EMERG, "======================================\n"); |
| 107 | print_trap_information(tf); |
| 108 | break; |
| 109 | } |
| 110 | } |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 111 | |
Maximilian Brune | 5d0fa0d | 2024-03-07 22:56:27 +0100 | [diff] [blame] | 112 | void (*trap_handler)(struct trapframe *tf) = default_trap_handler; |
Philipp Hug | 8e36539 | 2024-03-01 10:59:56 +0000 | [diff] [blame] | 113 | |
Maximilian Brune | 5d0fa0d | 2024-03-07 22:56:27 +0100 | [diff] [blame] | 114 | void default_trap_handler(struct trapframe *tf) |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 115 | { |
Ronald G. Minnich | d9307c2 | 2016-12-12 15:09:42 -0800 | [diff] [blame] | 116 | if (tf->cause & 0x8000000000000000ULL) { |
| 117 | interrupt_handler(tf); |
| 118 | return; |
| 119 | } |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 120 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 121 | switch (tf->cause) { |
Felix Singer | 6ff711c | 2023-12-08 10:39:44 +0100 | [diff] [blame] | 122 | case CAUSE_FETCH_ACCESS: |
| 123 | case CAUSE_ILLEGAL_INSTRUCTION: |
| 124 | case CAUSE_BREAKPOINT: |
| 125 | case CAUSE_LOAD_ACCESS: |
| 126 | case CAUSE_STORE_ACCESS: |
| 127 | case CAUSE_USER_ECALL: |
| 128 | case CAUSE_HYPERVISOR_ECALL: |
| 129 | case CAUSE_MACHINE_ECALL: |
| 130 | print_trap_information(tf); |
| 131 | break; |
| 132 | case CAUSE_SUPERVISOR_ECALL: |
| 133 | handle_sbi(tf); |
| 134 | return; |
Ronald G Minnich | 3ee97e4 | 2024-03-21 14:04:58 -0700 | [diff] [blame^] | 135 | case CAUSE_MISALIGNED_FETCH: |
Felix Singer | 6ff711c | 2023-12-08 10:39:44 +0100 | [diff] [blame] | 136 | case CAUSE_MISALIGNED_LOAD: |
| 137 | case CAUSE_MISALIGNED_STORE: |
| 138 | print_trap_information(tf); |
Felix Singer | 6ff711c | 2023-12-08 10:39:44 +0100 | [diff] [blame] | 139 | return; |
| 140 | default: |
| 141 | printk(BIOS_EMERG, "================================\n"); |
| 142 | printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); |
| 143 | printk(BIOS_EMERG, "================================\n"); |
| 144 | print_trap_information(tf); |
| 145 | break; |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 146 | } |
Jonathan Neuschäfer | 363526c | 2016-08-13 04:20:09 +0200 | [diff] [blame] | 147 | |
| 148 | die("Can't recover from trap. Halting.\n"); |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 149 | } |
| 150 | |
Xiang Wang | cda59b5 | 2018-08-09 16:20:35 +0800 | [diff] [blame] | 151 | /* This function used to redirect trap to s-mode. */ |
| 152 | void redirect_trap(void) |
| 153 | { |
Arthur Heymans | 917261d | 2023-04-19 21:25:08 +0200 | [diff] [blame] | 154 | write_csr(stval, read_csr(mtval)); |
Xiang Wang | cda59b5 | 2018-08-09 16:20:35 +0800 | [diff] [blame] | 155 | write_csr(sepc, read_csr(mepc)); |
| 156 | write_csr(scause, read_csr(mcause)); |
| 157 | write_csr(mepc, read_csr(stvec)); |
Jonathan Neuschäfer | b6648cd | 2016-08-22 19:37:15 +0200 | [diff] [blame] | 158 | |
Xiang Wang | cda59b5 | 2018-08-09 16:20:35 +0800 | [diff] [blame] | 159 | uintptr_t status = read_csr(mstatus); |
| 160 | uintptr_t mpp = EXTRACT_FIELD(status, MSTATUS_MPP); |
| 161 | status = INSERT_FIELD(status, MSTATUS_MPP, 1); |
| 162 | status = INSERT_FIELD(status, MSTATUS_SPP, mpp & 1); |
| 163 | write_csr(mstatus, status); |
Thaminda Edirisooriya | 95ba4c8 | 2015-08-26 14:54:31 -0700 | [diff] [blame] | 164 | } |