1. 3ee97e4 arch/riscv: remove misaligned load/store/fetch handling by Ronald G Minnich · 5 months ago
  2. 5d0fa0d arch/riscv: Remove typedefs by Maximilian Brune · 5 months ago
  3. 8e36539 riscv/mb/qemu: fix DRAM probing by Philipp Hug · 6 months ago
  4. 6ff711c arch/riscv: Use same indent levels for switch/case by Felix Singer · 8 months ago
  5. 917261d arch/riscv/trap_handler.c: Use new names for CSR by Arthur Heymans · 1 year, 4 months ago
  6. 2ba796e src/arch: Remove unnecessary space after casts by Elyes Haouas · 1 year, 9 months ago
  7. dd9edef arch/riscv/trap_handler: add missing types.h include by Felix Held · 3 years ago
  8. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  9. d1e50f9 src/arch/riscv: Convert to SPDX license header by Patrick Georgi · 4 years, 6 months ago
  10. a1e22b8 src: Use 'include <string.h>' when appropriate by Elyes HAOUAS · 5 years ago
  11. 909be6a riscv: Show hart id in trap handler by Philipp Hug · 6 years ago
  12. 0ce41f1 src: Add required space after "switch" by Elyes HAOUAS · 6 years ago
  13. 22e0c56 riscv: add support for supervisor binary interface (SBI) by Xiang Wang · 6 years ago
  14. 1ed082b riscv: simplify timer interrupt handling by Philipp Hug · 6 years ago
  15. cda59b5 riscv: update misaligned memory access exception handling by Xiang Wang · 6 years ago
  16. a5c49b8 arch/riscv: Update encoding.h and adjust related code by Jonathan Neuschäfer · 7 years ago
  17. c0c31b6 riscv: Remove config string support by Jonathan Neuschäfer · 7 years ago
  18. 3ca8b59 arch/riscv: Remove the current SBI implementation by Jonathan Neuschäfer · 7 years ago
  19. b0de851 arch/riscv: Return from trap_handler instead of jumping out by Jonathan Neuschäfer · 7 years ago
  20. 3f75f5d arch/riscv: Unify trap return by Jonathan Neuschäfer · 7 years ago
  21. c90f1d7b arch/riscv: gettimer: Don't use the config string by Jonathan Neuschäfer · 7 years ago
  22. 5a01d6a arch/riscv: trap handler: Print load/store access width in bits by Jonathan Neuschäfer · 7 years ago
  23. e18e642 src: change coreboot to lowercase by Martin Roth · 7 years ago
  24. c5ebb1d riscv: Move mcall numbers to mcall.h, adjust their names by Jonathan Neuschäfer · 8 years ago
  25. 6f3a53b riscv: get SBI calls to work by Ronald G. Minnich · 8 years ago
  26. d9307c2 riscv: Add support for timer interrupts by Ronald G. Minnich · 8 years ago
  27. 99f2f11 riscv: Unify SBI call implementations under arch/riscv/ by Jonathan Neuschäfer · 8 years ago
  28. 571c230 riscv: Add a bandaid for the new toolchain by Ronald G. Minnich · 8 years ago
  29. 0bc12ab arch/riscv: In trap handler, don't print SP twice by Jonathan Neuschäfer · 8 years ago 4.5
  30. 2f72a61 arch/riscv: Visually align trap frame information by Jonathan Neuschäfer · 8 years ago
  31. 2af174a riscv and power8: Convert printk/while(1) to die by Jonathan Neuschäfer · 8 years ago
  32. a1e3924 arch/riscv: Add missing "break;" by Jonathan Neuschäfer · 8 years ago
  33. 857e33e arch/riscv: Implement the SBI again by Jonathan Neuschäfer · 8 years ago
  34. b6648cd arch/riscv: Fix unaligned memory access emulation by Jonathan Neuschäfer · 8 years ago
  35. 363526c arch/riscv: Improve and refactor trap handling diagnostics by Jonathan Neuschäfer · 8 years ago
  36. 1b1d4b7 arch/riscv: Enable unaligned load handling by Jonathan Neuschäfer · 8 years ago
  37. fefc77a arch/riscv: Show fault PC and load address on load access faults by Jonathan Neuschäfer · 8 years ago
  38. 38cd375 RISC-V: Add more debug info to debug printks by Andrew Waterman · 9 years ago
  39. f16d904 RISC-V: Make inline asm usage safer by Andrew Waterman · 9 years ago
  40. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  41. d9653e1 riscv-trap-handling: Add functionality, prevent stack corruption by Thaminda Edirisooriya · 9 years ago
  42. 95ba4c8 riscv-trap-handling: Add implementation for trap calls in riscv by Thaminda Edirisooriya · 9 years ago