Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <cpu/cpu.h> |
| 19 | #include <cpu/intel/microcode.h> |
| 20 | #include <cpu/intel/turbo.h> |
| 21 | #include <cpu/x86/cache.h> |
| 22 | #include <cpu/x86/lapic.h> |
| 23 | #include <cpu/x86/mp.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <cpu/x86/smm.h> |
Lee Leahy | 94b856e | 2015-10-15 12:07:03 -0700 | [diff] [blame] | 27 | #include <fsp/memmap.h> |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 28 | #include <reg_script.h> |
Chiranjeevi Rapolu | fd016a4 | 2015-08-11 14:09:46 -0700 | [diff] [blame] | 29 | #include <soc/iosf.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 30 | #include <soc/msr.h> |
| 31 | #include <soc/pattrs.h> |
| 32 | #include <soc/ramstage.h> |
| 33 | #include <soc/smm.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 35 | |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 36 | /* Core level MSRs */ |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 37 | static const struct reg_script core_msr_script[] = { |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 38 | /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ |
| 39 | REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), |
| 40 | REG_MSR_RMW(MSR_POWER_MISC, |
| 41 | ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), |
| 42 | /* Disable C1E */ |
| 43 | REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), |
| 44 | REG_MSR_OR(MSR_POWER_MISC, 0x44), |
| 45 | REG_SCRIPT_END |
| 46 | }; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 47 | |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 48 | static void soc_core_init(device_t cpu) |
| 49 | { |
| 50 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 51 | __FILE__, __func__, dev_name(cpu)); |
| 52 | printk(BIOS_DEBUG, "Init Braswell core.\n"); |
| 53 | |
| 54 | /* |
| 55 | * The turbo disable bit is actually scoped at building |
| 56 | * block level -- not package. For non-bsp cores that are within a |
| 57 | * building block enable turbo. The cores within the BSP's building |
| 58 | * block will just see it already enabled and move on. |
| 59 | */ |
| 60 | if (lapicid()) |
| 61 | enable_turbo(); |
| 62 | |
| 63 | /* Set core MSRs */ |
| 64 | reg_script_run(core_msr_script); |
| 65 | |
| 66 | /* Set this core to max frequency ratio */ |
| 67 | set_max_freq(); |
| 68 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 69 | |
| 70 | static struct device_operations cpu_dev_ops = { |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 71 | .init = soc_core_init, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | static struct cpu_device_id cpu_table[] = { |
Divya Sasidharan | 1ff0f54 | 2015-10-11 11:22:21 -0700 | [diff] [blame] | 75 | { X86_VENDOR_INTEL, 0x406C4 }, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 76 | { X86_VENDOR_INTEL, 0x406C3 }, |
| 77 | { X86_VENDOR_INTEL, 0x406C2 }, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 78 | { 0, 0 }, |
| 79 | }; |
| 80 | |
| 81 | static const struct cpu_driver driver __cpu_driver = { |
| 82 | .ops = &cpu_dev_ops, |
| 83 | .id_table = cpu_table, |
| 84 | }; |
| 85 | |
| 86 | |
| 87 | /* |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 88 | * MP and SMM loading initialization. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 89 | */ |
| 90 | |
| 91 | struct smm_relocation_attrs { |
| 92 | uint32_t smbase; |
| 93 | uint32_t smrr_base; |
| 94 | uint32_t smrr_mask; |
| 95 | }; |
| 96 | |
| 97 | static struct smm_relocation_attrs relo_attrs; |
| 98 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 99 | /* Package level MSRs */ |
| 100 | static const struct reg_script package_msr_script[] = { |
| 101 | /* Set Package TDP to ~7W */ |
| 102 | REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), |
| 103 | REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), |
| 104 | REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), |
| 105 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), |
| 106 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), |
| 107 | REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), |
| 108 | REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), |
| 109 | REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), |
| 110 | REG_SCRIPT_END |
| 111 | }; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 113 | static void pre_mp_init(void) |
| 114 | { |
| 115 | uint32_t bsmrwac; |
| 116 | |
| 117 | /* Set up MTRRs based on physical address size. */ |
| 118 | x86_setup_mtrrs_with_detect(); |
| 119 | x86_mtrr_check(); |
| 120 | |
| 121 | /* |
| 122 | * Configure the BUNIT to allow dirty cache line evictions in non-SMM |
| 123 | * mode for the lines that were dirtied while in SMM mode. Otherwise |
| 124 | * the writes would be silently dropped. |
| 125 | */ |
| 126 | bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; |
| 127 | iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); |
| 128 | |
| 129 | /* Set package MSRs */ |
| 130 | reg_script_run(package_msr_script); |
| 131 | |
| 132 | /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ |
| 133 | enable_turbo(); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 134 | } |
| 135 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 136 | static int get_cpu_count(void) |
| 137 | { |
| 138 | const struct pattrs *pattrs = pattrs_get(); |
| 139 | |
| 140 | return pattrs->num_cpus; |
| 141 | } |
| 142 | |
| 143 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 144 | size_t *smm_save_state_size) |
| 145 | { |
| 146 | void *smm_base; |
| 147 | size_t smm_size; |
| 148 | |
| 149 | /* All range registers are aligned to 4KiB */ |
| 150 | const uint32_t rmask = ~((1 << 12) - 1); |
| 151 | |
| 152 | /* Initialize global tracking state. */ |
| 153 | smm_region(&smm_base, &smm_size); |
| 154 | relo_attrs.smbase = (uint32_t)smm_base; |
| 155 | relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; |
| 156 | relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; |
| 157 | relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; |
| 158 | |
| 159 | *perm_smbase = relo_attrs.smbase; |
| 160 | *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; |
| 161 | *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 162 | } |
| 163 | |
| 164 | /* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ |
| 165 | static int adjust_apic_id(int index, int apic_id) |
| 166 | { |
| 167 | return 2 * index; |
| 168 | } |
| 169 | |
| 170 | static void get_microcode_info(const void **microcode, int *parallel) |
| 171 | { |
| 172 | const struct pattrs *pattrs = pattrs_get(); |
| 173 | |
| 174 | *microcode = pattrs->microcode_patch; |
| 175 | *parallel = 1; |
| 176 | } |
| 177 | |
| 178 | static void per_cpu_smm_trigger(void) |
| 179 | { |
| 180 | const struct pattrs *pattrs = pattrs_get(); |
| 181 | msr_t msr_value; |
| 182 | |
| 183 | /* Need to make sure that all cores have microcode loaded. */ |
| 184 | msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); |
| 185 | if (msr_value.hi == 0) |
| 186 | intel_microcode_load_unlocked(pattrs->microcode_patch); |
| 187 | |
| 188 | /* Relocate SMM space. */ |
| 189 | smm_initiate_relocation(); |
| 190 | |
| 191 | /* Load microcode after SMM relocation. */ |
| 192 | intel_microcode_load_unlocked(pattrs->microcode_patch); |
| 193 | } |
| 194 | |
| 195 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 196 | uintptr_t staggered_smbase) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 197 | { |
| 198 | msr_t smrr; |
| 199 | em64t100_smm_state_save_area_t *smm_state; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 200 | |
| 201 | /* Set up SMRR. */ |
| 202 | smrr.lo = relo_attrs.smrr_base; |
| 203 | smrr.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 204 | wrmsr(SMRR_PHYS_BASE, smrr); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 205 | smrr.lo = relo_attrs.smrr_mask; |
| 206 | smrr.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 207 | wrmsr(SMRR_PHYS_MASK, smrr); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 208 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 209 | smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); |
| 210 | smm_state->smbase = staggered_smbase; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 211 | } |
| 212 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 213 | static const struct mp_ops mp_ops = { |
| 214 | .pre_mp_init = pre_mp_init, |
| 215 | .get_cpu_count = get_cpu_count, |
| 216 | .get_smm_info = get_smm_info, |
| 217 | .get_microcode_info = get_microcode_info, |
| 218 | .adjust_cpu_apic_entry = adjust_apic_id, |
| 219 | .pre_mp_smm_init = southcluster_smm_clear_state, |
| 220 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 221 | .relocation_handler = relocation_handler, |
| 222 | .post_mp_init = southcluster_smm_enable_smi, |
| 223 | }; |
| 224 | |
| 225 | void soc_init_cpus(device_t dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 226 | { |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 227 | struct bus *cpu_bus = dev->link_list; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 228 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 229 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 230 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 231 | |
Aaron Durbin | bbe4a7e | 2016-05-03 15:47:48 -0500 | [diff] [blame] | 232 | if (mp_init_with_smm(cpu_bus, &mp_ops)) { |
| 233 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 234 | } |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 235 | } |