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review.coreboot.org / coreboot / 3dbea29ee65c99ae09690765f20869b46464e66a / src / soc / intel / braswell / cpu.c
  1. bbe4a7e soc/intel/braswell: convert to using common MP and SMM init by Aaron Durbin · 8 years ago
  2. 0e55632 cpu/x86/mp_init: remove unused callback arguments by Aaron Durbin · 8 years ago
  3. 2a08137 x86 chipsets: utilize x86_setup_mtrrs_with_detect() by Aaron Durbin · 8 years ago
  4. 1ff0f54 soc/braswell: Add CPUID for D0 stepping by Divya Sasidharan · 9 years ago
  5. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  6. 94b856e FSP 1.1: Move common FSP code by Lee Leahy · 9 years ago
  7. 86091f9 cpu/mtrr.h: Fix macro names for MTRR registers by Alexandru Gagniuc · 9 years ago
  8. fd016a4 intel/braswell: allow dirty cache line evictions for SMRAM to stick by Chiranjeevi Rapolu · 9 years ago
  9. acb9c0b Braswell: Update to end of June. by Lee Leahy · 9 years ago
  10. 3247172 Braswell: Add Braswell SOC support by Lee Leahy · 9 years ago
  11. 25509ee Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  12. 77ff0b1 Braswell: Use Baytrail as Comparison Base by Lee Leahy · 9 years ago