blob: bc5d0669da940c10250aae80db496c6d2a6cb787 [file] [log] [blame]
Julius Wernerec5e5e02014-08-20 15:29:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Julius Wernerec5e5e02014-08-20 15:29:56 -070014 */
15
16#include <memlayout.h>
17
18#include <arch/header.ld>
19
20/*
21 * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock
22 * must be placed after that. After the handoff, the space can be reclaimed.
23 */
24
25SECTIONS
26{
27 SRAM_START(0x2020000)
28 /* 17K hole, includes BL1 */
Elyes HAOUAS3d450002018-08-09 18:55:58 +020029 /* Bootblock is preceded by 16 byte variable length BL2 checksum. */
Julius Wernerec5e5e02014-08-20 15:29:56 -070030 BOOTBLOCK(0x2024410, 32K - 16)
31 /* 15K hole */
32 ROMSTAGE(0x2030000, 128K)
33 /* 32K hole */
34 TTB(0x2058000, 16K)
35 PRERAM_CBFS_CACHE(0x205C000, 76K)
36 STACK(0x206F000, 16K)
37 /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
38 * seem to be implemented right now? */
39 SRAM_END(0x2074000)
40
41 DRAM_START(0x20000000)
42 RAMSTAGE(0x20000000, 128K)
43 POSTRAM_CBFS_CACHE(0x21000000, 8M)
44 DMA_COHERENT(0x77300000, 1M)
45}