blob: 3259ff907b74a11d76471b3d1d38a326718bda24 [file] [log] [blame]
Julius Wernerec5e5e02014-08-20 15:29:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <memlayout.h>
21
22#include <arch/header.ld>
23
24/*
25 * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock
26 * must be placed after that. After the handoff, the space can be reclaimed.
27 */
28
29SECTIONS
30{
31 SRAM_START(0x2020000)
32 /* 17K hole, includes BL1 */
33 /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */
34 BOOTBLOCK(0x2024410, 32K - 16)
35 /* 15K hole */
36 ROMSTAGE(0x2030000, 128K)
37 /* 32K hole */
38 TTB(0x2058000, 16K)
39 PRERAM_CBFS_CACHE(0x205C000, 76K)
40 STACK(0x206F000, 16K)
41 /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
42 * seem to be implemented right now? */
43 SRAM_END(0x2074000)
44
45 DRAM_START(0x20000000)
46 RAMSTAGE(0x20000000, 128K)
47 POSTRAM_CBFS_CACHE(0x21000000, 8M)
48 DMA_COHERENT(0x77300000, 1M)
49}