Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <stdint.h> |
| 19 | #include "x4x.h" |
| 20 | |
| 21 | const struct dll_setting default_ddr2_667_ctrl[7] = { |
| 22 | /* tap pi db delay coarse*/ |
| 23 | {13, 0, 1, 0, 0, 0}, /* clkset0 */ |
| 24 | {4, 1, 0, 0, 0, 0}, /* ctrl0 */ |
| 25 | {13, 0, 1, 0, 0, 0}, /* clkset1 */ |
| 26 | {4, 5, 0, 0, 0, 0}, /* cmd */ |
| 27 | {4, 1, 0, 0, 0, 0}, /* ctrl1 */ |
| 28 | {4, 1, 0, 0, 0, 0}, /* ctrl2 */ |
| 29 | {4, 1, 0, 0, 0, 0}, /* ctrl3 */ |
| 30 | }; |
| 31 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 32 | const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 33 | {1, 5, 1, 1, 1, 0}, |
| 34 | {1, 6, 1, 1, 1, 0}, |
| 35 | {2, 0, 1, 1, 1, 0}, |
| 36 | {2, 1, 1, 1, 1, 0}, |
| 37 | {2, 1, 1, 1, 1, 0}, |
| 38 | {14, 6, 1, 0, 0, 0}, |
| 39 | {14, 3, 1, 0, 0, 0}, |
| 40 | {14, 0, 1, 0, 0, 0}, |
| 41 | }; |
| 42 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 43 | const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 44 | {9, 0, 0, 0, 1, 0}, |
| 45 | {9, 1, 0, 0, 1, 0}, |
| 46 | {9, 2, 0, 0, 1, 0}, |
| 47 | {9, 2, 0, 0, 1, 0}, |
| 48 | {9, 1, 0, 0, 1, 0}, |
| 49 | {6, 4, 0, 0, 1, 0}, |
| 50 | {6, 2, 0, 0, 1, 0}, |
| 51 | {5, 4, 0, 0, 1, 0} |
| 52 | }; |
| 53 | |
| 54 | const struct dll_setting default_ddr2_800_ctrl[7] = { |
| 55 | /* tap pi db delay coarse */ |
| 56 | {11, 5, 1, 0, 0, 0}, |
| 57 | {0, 5, 1, 1, 0, 0}, |
| 58 | {11, 5, 1, 0, 0, 0}, |
| 59 | {1, 4, 1, 1, 0, 0}, |
| 60 | {0, 5, 1, 1, 0, 0}, |
| 61 | {0, 5, 1, 1, 0, 0}, |
| 62 | {0, 5, 1, 1, 0, 0}, |
| 63 | }; |
| 64 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 65 | const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 66 | {2, 5, 1, 1, 1, 0}, |
| 67 | {2, 6, 1, 1, 1, 0}, |
| 68 | {3, 0, 1, 1, 1, 0}, |
| 69 | {3, 0, 1, 1, 1, 0}, |
| 70 | {3, 3, 1, 1, 1, 0}, |
| 71 | {2, 0, 1, 1, 1, 0}, |
| 72 | {1, 3, 1, 1, 1, 0}, |
| 73 | {0, 3, 1, 1, 1, 0}, |
| 74 | }; |
| 75 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 76 | const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 77 | {9, 3, 0, 0, 1, 0}, |
| 78 | {9, 4, 0, 0, 1, 0}, |
| 79 | {9, 5, 0, 0, 1, 0}, |
| 80 | {9, 6, 0, 0, 1, 0}, |
| 81 | {10, 0, 0, 0, 1, 0}, |
| 82 | {8, 1, 0, 0, 1, 0}, |
| 83 | {7, 5, 0, 0, 1, 0}, |
| 84 | {6, 2, 0, 0, 1, 0} |
| 85 | }; |
| 86 | |
| 87 | const struct dll_setting default_ddr3_800_ctrl[2][7] = { |
| 88 | { /* 1N */ |
| 89 | /* tap pi db(2) delay coarse */ |
| 90 | {8, 2, 0, 0, 0, 0}, |
| 91 | {8, 4, 0, 0, 0, 0}, |
| 92 | {9, 5, 0, 0, 0, 0}, |
| 93 | {6, 1, 0, 0, 0, 0}, |
| 94 | {8, 4, 0, 0, 0, 0}, |
| 95 | {10, 0, 0, 0, 0, 0}, |
| 96 | {10, 0, 0, 0, 0, 0}, }, |
| 97 | { /* 2N */ |
| 98 | {2, 2, 1, 1, 0, 0}, |
| 99 | {2, 4, 1, 1, 0, 0}, |
| 100 | {3, 5, 0, 0, 0, 0}, |
| 101 | {3, 2, 1, 1, 0, 0}, |
| 102 | {2, 4, 1, 1, 0, 0}, |
| 103 | {3, 6, 0, 0, 0, 0}, |
| 104 | {3, 6, 0, 0, 0, 0}, } |
| 105 | }; |
| 106 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 107 | const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 108 | { /* 1N */ |
| 109 | {12, 0, 1, 0, 0, 0}, |
| 110 | {1, 1, 1, 1, 1, 0}, |
| 111 | {2, 4, 1, 1, 1, 0}, |
| 112 | {3, 5, 0, 0, 1, 0}, |
| 113 | {4, 3, 0, 0, 1, 0}, |
| 114 | {5, 2, 0, 0, 1, 0}, |
| 115 | {6, 1, 0, 0, 1, 0}, |
| 116 | {6, 4, 0, 0, 1, 0}, }, |
| 117 | { /* 2N */ |
| 118 | {5, 6, 0, 0, 0, 0}, |
| 119 | {8, 0, 0, 0, 0, 0}, |
| 120 | {9, 4, 0, 0, 0, 0}, |
| 121 | {10, 4, 1, 0, 0, 0}, |
| 122 | {11, 3, 1, 0, 0, 0}, |
| 123 | {12, 1, 1, 0, 0, 0}, |
| 124 | {0, 1, 1, 1, 1, 0}, |
| 125 | {0, 3, 1, 1, 1, 0}, } |
| 126 | }; |
| 127 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 128 | const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 129 | { /* 1N */ |
| 130 | {4, 1, 0, 0, 1, 0}, |
| 131 | {6, 4, 0, 0, 1, 0}, |
| 132 | {8, 1, 0, 0, 1, 0}, |
| 133 | {8, 6, 0, 0, 1, 0}, |
| 134 | {9, 5, 0, 0, 1, 0}, |
| 135 | {10, 2, 0, 0, 1, 0}, |
| 136 | {10, 6, 1, 0, 1, 0}, |
| 137 | {11, 4, 1, 0, 1, 0} }, |
| 138 | { /* 2N */ |
| 139 | {11, 0, 1, 0, 0, 0}, |
| 140 | {0, 3, 1, 1, 1, 0}, |
| 141 | {2, 1, 1, 1, 1, 0}, |
| 142 | {2, 5, 1, 1, 1, 0}, |
| 143 | {3, 5, 0, 0, 1, 0}, |
| 144 | {4, 2, 0, 0, 1, 0}, |
| 145 | {4, 6, 0, 0, 1, 0}, |
| 146 | {5, 4, 0, 0, 1, 0}, } |
| 147 | }; |
| 148 | |
| 149 | const struct dll_setting default_ddr3_1067_ctrl[2][7] = { |
| 150 | { /* 1N */ |
| 151 | {8, 5, 0, 0, 0, 0}, |
| 152 | {7, 6, 0, 0, 0, 0}, |
| 153 | {10, 2, 1, 0, 0, 0}, |
| 154 | {4, 4, 0, 0, 0, 0}, |
| 155 | {7, 6, 0, 0, 0, 0}, |
| 156 | {9, 2, 1, 0, 0, 0}, |
| 157 | {9, 2, 1, 0, 0, 0}, }, |
| 158 | { /* 2N */ |
| 159 | {1, 5, 1, 1, 0, 0}, |
| 160 | {0, 6, 1, 1, 0, 0}, |
| 161 | {3, 2, 0, 0, 0, 0}, |
| 162 | {2, 6, 1, 1, 0, 0}, |
| 163 | {0, 6, 1, 1, 0, 0}, |
| 164 | {2, 2, 1, 1, 0, 0}, |
| 165 | {2, 2, 1, 1, 0, 0}, } |
| 166 | }; |
| 167 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 168 | const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 169 | { /* 1N */ |
| 170 | {2, 5, 1, 1, 1, 0}, |
| 171 | {5, 1, 0, 0, 1, 0}, |
| 172 | {6, 6, 0, 0, 1, 0}, |
| 173 | {8, 0, 0, 0, 1, 0}, |
| 174 | {8, 6, 0, 0, 1, 0}, |
| 175 | {9, 6, 1, 0, 1, 0}, |
| 176 | {10, 6, 1, 0, 1, 0}, |
| 177 | {0, 1, 1, 1, 0, 1}, }, |
| 178 | { /* 2N */ |
| 179 | {6, 4, 0, 0, 0, 0}, |
| 180 | {9, 1, 1, 0, 0, 0}, |
| 181 | {10, 6, 1, 0, 0, 0}, |
| 182 | {1, 0, 1, 1, 1, 0}, |
| 183 | {1, 6, 1, 1, 1, 0}, |
| 184 | {2, 5, 1, 1, 1, 0}, |
| 185 | {3, 5, 0, 0, 1, 0}, |
| 186 | {4, 1, 0, 0, 1, 0}, |
| 187 | } |
| 188 | }; |
| 189 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 190 | const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 191 | { /* 1N */ |
| 192 | {6, 5, 0, 0, 1, 0}, |
| 193 | {9, 3, 1, 0, 1, 0}, |
| 194 | {0, 2, 1, 1, 0, 1}, |
| 195 | {1, 0, 1, 1, 0, 1}, |
| 196 | {2, 0, 1, 1, 0, 1}, |
| 197 | {2, 5, 1, 1, 0, 1}, |
| 198 | {3, 2, 0, 0, 0, 1}, |
| 199 | {4, 1, 0, 0, 0, 1}, }, |
| 200 | { /* 2N */ |
| 201 | {10, 5, 1, 0, 0, 0}, |
| 202 | {2, 3, 1, 1, 1, 0}, |
| 203 | {4, 1, 0, 0, 1, 0}, |
| 204 | {5, 0, 0, 0, 1, 0}, |
| 205 | {6, 0, 0, 0, 1, 0}, |
| 206 | {6, 5, 0, 0, 1, 0}, |
| 207 | {7, 2, 0, 0, 1, 0}, |
| 208 | {8, 1, 0, 0, 1, 0}, |
| 209 | } |
| 210 | }; |
| 211 | |
| 212 | const struct dll_setting default_ddr3_1333_ctrl[2][7] = { |
| 213 | { /* 1N */ |
| 214 | {8, 5, 0, 0, 0, 0}, |
| 215 | {9, 0, 1, 0, 0, 0}, |
| 216 | {10, 2, 1, 0, 0, 0}, |
| 217 | {0, 0, 1, 1, 0, 0}, |
| 218 | {9, 0, 1, 0, 0, 0}, |
| 219 | {10, 4, 1, 0, 0, 0}, |
| 220 | {10, 4, 1, 0, 0, 0}, }, |
| 221 | { /* 2N */ |
| 222 | {1, 6, 1, 1, 0, 0}, |
| 223 | {2, 2, 1, 1, 0, 0}, |
| 224 | {4, 2, 0, 0, 0, 0}, |
| 225 | {3, 1, 1, 1, 0, 0}, |
| 226 | {2, 2, 1, 1, 0, 0}, |
| 227 | {4, 5, 0, 0, 0, 0}, |
| 228 | {4, 5, 0, 0, 0, 0}, } |
| 229 | }; |
| 230 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 231 | const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 232 | { /* 1N */ |
| 233 | {2, 4, 1, 1, 1, 0}, |
| 234 | {5, 1, 0, 0, 1, 0}, |
| 235 | {6, 6, 0, 0, 1, 0}, |
| 236 | {8, 0, 0, 0, 1, 0}, |
| 237 | {8, 6, 0, 0, 1, 0}, |
| 238 | {9, 5, 1, 0, 1, 0}, |
| 239 | {10, 6, 1, 0, 1, 0}, |
| 240 | {0, 1, 1, 1, 0, 1}, }, |
| 241 | { /* 2N */ |
| 242 | {10, 4, 0, 0, 0, 0}, |
| 243 | {0, 3, 1, 1, 1, 0}, |
| 244 | {3, 2, 1, 1, 1, 0}, |
| 245 | {5, 0, 0, 0, 1, 0}, |
| 246 | {6, 1, 0, 0, 1, 0}, |
| 247 | {7, 4, 0, 0, 1, 0}, |
| 248 | {9, 2, 0, 0, 1, 0}, |
| 249 | {9, 6, 0, 0, 1, 0}, } |
| 250 | }; |
| 251 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 252 | const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 253 | { /* 1N */ |
| 254 | {6, 5, 0, 0, 1, 0}, |
| 255 | {9, 3, 1, 0, 1, 0}, |
| 256 | {0, 2, 1, 1, 0, 1}, |
| 257 | {1, 0, 1, 1, 0, 1}, |
| 258 | {2, 0, 1, 1, 0, 1}, |
| 259 | {2, 5, 1, 1, 0, 1}, |
| 260 | {3, 2, 0, 0, 0, 1}, |
| 261 | {4, 1, 0, 0, 0, 1}, }, |
| 262 | { /* 2N */ |
| 263 | {1, 3, 1, 1, 1, 0}, |
| 264 | {5, 6, 0, 0, 1, 0}, |
| 265 | {8, 5, 0, 0, 1, 0}, |
| 266 | {10, 2, 0, 0, 1, 0}, |
| 267 | {11, 1, 0, 0, 1, 0}, |
| 268 | {12, 3, 1, 0, 1, 0}, |
| 269 | {13, 6, 1, 0, 1, 0}, |
| 270 | {0, 3, 1, 1, 0, 1}, } |
| 271 | }; |
Arthur Heymans | f128726 | 2017-12-25 18:30:01 +0100 | [diff] [blame] | 272 | |
| 273 | const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */ |
| 274 | {0x00, 0x00, 0x00, 0x00}, /* NC_NC */ |
| 275 | {0x11, 0x00, 0x00, 0x00}, /* 8S_NC */ |
| 276 | {0x11, 0x11, 0x00, 0x00}, /* 8D_NC */ |
| 277 | {0x11, 0x00, 0x00, 0x00}, /* 16S_NC */ |
| 278 | {0x00, 0x00, 0x11, 0x00}, /* NC_8S */ |
| 279 | {0x81, 0x00, 0x81, 0x00}, /* 8S_8S */ |
| 280 | {0x81, 0x81, 0x81, 0x00}, /* 8D_8S */ |
| 281 | {0x81, 0x00, 0x81, 0x00}, /* 16S_8S */ |
| 282 | {0x00, 0x00, 0x11, 0x11}, /* NC_8D */ |
| 283 | {0x81, 0x00, 0x81, 0x81}, /* 8S_8D */ |
| 284 | {0x81, 0x81, 0x81, 0x81}, /* 8D_8D */ |
| 285 | {0x81, 0x00, 0x81, 0x81}, /* 16S_8D */ |
| 286 | {0x00, 0x00, 0x11, 0x00}, /* NC_16S */ |
| 287 | {0x81, 0x00, 0x81, 0x00}, /* 8S_16S */ |
| 288 | {0x81, 0x81, 0x81, 0x00}, /* 8D_16S */ |
| 289 | {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ |
| 290 | }; |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 291 | |
Arthur Heymans | 0d28495 | 2017-05-25 19:55:52 +0200 | [diff] [blame] | 292 | const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */ |
| 293 | { /* FSB DDR */ |
| 294 | {{0x3, 0x5}, /* 800 667 */ |
| 295 | {0x3, 0x4}, /* 800 800 */ |
| 296 | }, |
| 297 | {{0x4, 0x8}, /* 1067 667 */ |
| 298 | {0x4, 0x6}, /* 1067 800 */ |
| 299 | {0x3, 0x5}, /* 1067 1066 */ |
| 300 | }, |
| 301 | {{0x5, 0x9}, /* 1333 667 */ |
| 302 | {0x4, 0x7}, /* 1333 800 */ |
| 303 | {0x4, 0x7}, /* 1333 1066 */ |
| 304 | {0x4, 0x7} /* 1333 1333 */ |
| 305 | }, |
| 306 | }; |
| 307 | |
| 308 | |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 309 | const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ |
| 310 | /* 115h[15:0] 117h[23:0] */ |
| 311 | { /* 1N mode */ |
| 312 | { /* DDR3 800MHz */ |
| 313 | {0x0189, 0x000aaa}, /* CAS = 5 */ |
| 314 | {0x0189, 0x101aaa}, /* CAS = 6 */ |
| 315 | }, |
| 316 | { /* DDR3 1067MHz */ |
| 317 | {0x0000, 0x000000}, /* CAS = 5 - Not supported */ |
| 318 | {0x0089, 0x000bbb}, /* CAS = 6 */ |
| 319 | {0x0099, 0x101bbb}, /* CAS = 7 */ |
| 320 | {0x0099, 0x202bbb} /* CAS = 8 */ |
| 321 | },{ /* DDR3 1333 */ |
| 322 | {0x0000, 0x000000}, /* CAS = 5 - Not supported */ |
| 323 | {0x0000, 0x000000}, /* CAS = 6 - Not supported */ |
| 324 | {0x0000, 0x000000}, /* CAS = 7 - Not supported */ |
| 325 | {0x129a, 0x0078dc}, /* CAS = 8 */ |
| 326 | {0x028a, 0x0078dc}, /* CAS = 9 */ |
| 327 | {0x028a, 0x1088dc}, /* CAS = 10 */ |
| 328 | }, |
| 329 | }, |
| 330 | { /* 2N mode */ |
| 331 | { /* DDR3 800MHz */ |
| 332 | {0x0189, 0x000aaa}, /* CAS = 5 */ |
| 333 | {0x0189, 0x101aaa}, /* CAS = 6 */ |
| 334 | {0x0000, 0x000000}, /* CAS = 7 - Not supported */ |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame^] | 335 | {0x0000, 0x000000} /* CAS = 8 - Not supported */ |
Arthur Heymans | 3fa103a | 2017-05-25 19:54:49 +0200 | [diff] [blame] | 336 | }, |
| 337 | { /* DDR3 1067 */ |
| 338 | {0x0000, 0x000000}, /* CAS = 5 - Not supported */ |
| 339 | {0x0089, 0x000bbb}, /* CAS = 6 */ |
| 340 | {0x0099, 0x101bbb}, /* CAS = 7 */ |
| 341 | {0x0099, 0x202bbb} /* CAS = 8 */ |
| 342 | },{ /* DDR3 1333MHz */ |
| 343 | {0x0000, 0x000000}, /* CAS = 5 - Not supported */ |
| 344 | {0x0000, 0x000000}, /* CAS = 6 - Not supported */ |
| 345 | {0x0000, 0x000000}, /* CAS = 7 - Not supported */ |
| 346 | {0x019a, 0x0078dc}, /* CAS = 8 */ |
| 347 | {0x019a, 0x1088dc}, /* CAS = 9 */ |
| 348 | {0x019a, 0x2098dc}, /* CAS = 10 */ |
| 349 | }, |
| 350 | } |
| 351 | }; |
| 352 | |
| 353 | const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */ |
| 354 | /* DDR3 800MHz */ |
| 355 | {0x78, /* CAS = 5 */ |
| 356 | 0x89}, /* CAS = 6 */ |
| 357 | /* DDR3 1066 */ |
| 358 | {0x00, /* CAS = 5 - Not supported */ |
| 359 | 0xff, /* CAS = 6 */ |
| 360 | 0x8a, /* CAS = 7 */ |
| 361 | 0x9a}, /* CAS = 8 */ |
| 362 | /* DDR3 1333 */ |
| 363 | {0x00, /* CAS = 5 - Not supported */ |
| 364 | 0x00, /* CAS = 6 - Not supported */ |
| 365 | 0xff, /* CAS = 7 - Not supported */ |
| 366 | 0xff, /* CAS = 8 */ |
| 367 | 0xff, /* CAS = 9 */ |
| 368 | 0xff}, /* CAS = 10 */ |
| 369 | }; |
| 370 | |
| 371 | const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */ |
| 372 | /* DDR3 800MHz */ |
| 373 | {0x9bbb, /* CAS = 5 */ |
| 374 | 0x8bbb}, /* CAS = 6 */ |
| 375 | /* DDR3 1066MHz */ |
| 376 | {0x0000, /* CAS = 5 - Not supported */ |
| 377 | 0x9baa, /* CAS = 6 */ |
| 378 | 0x8caa, /* CAS = 7 */ |
| 379 | 0x7daa}, /* CAS = 8 */ |
| 380 | |
| 381 | /* DDR3 1333MHz */ |
| 382 | {0x0000, /* CAS = 5 - Not supported */ |
| 383 | 0x0000, /* CAS = 6 - Not supported */ |
| 384 | 0x0000, /* CAS = 7 - Not supported */ |
| 385 | 0xaecb, /* CAS = 8 */ |
| 386 | 0x9fcb, /* CAS = 9 */ |
| 387 | 0x8fcb}, /* CAS = 10 */ |
| 388 | }; |