nb/intel/x4x: Add DDR3 JEDEC init
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)
This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.
The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.
Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index 9a39b28..47d8a98 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -269,3 +269,22 @@
{13, 6, 1, 0, 1, 0},
{0, 3, 1, 1, 0, 1}, }
};
+
+const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
+ {0x00, 0x00, 0x00, 0x00}, /* NC_NC */
+ {0x11, 0x00, 0x00, 0x00}, /* 8S_NC */
+ {0x11, 0x11, 0x00, 0x00}, /* 8D_NC */
+ {0x11, 0x00, 0x00, 0x00}, /* 16S_NC */
+ {0x00, 0x00, 0x11, 0x00}, /* NC_8S */
+ {0x81, 0x00, 0x81, 0x00}, /* 8S_8S */
+ {0x81, 0x81, 0x81, 0x00}, /* 8D_8S */
+ {0x81, 0x00, 0x81, 0x00}, /* 16S_8S */
+ {0x00, 0x00, 0x11, 0x11}, /* NC_8D */
+ {0x81, 0x00, 0x81, 0x81}, /* 8S_8D */
+ {0x81, 0x81, 0x81, 0x81}, /* 8D_8D */
+ {0x81, 0x00, 0x81, 0x81}, /* 16S_8D */
+ {0x00, 0x00, 0x11, 0x00}, /* NC_16S */
+ {0x81, 0x00, 0x81, 0x00}, /* 8S_16S */
+ {0x81, 0x81, 0x81, 0x00}, /* 8D_16S */
+ {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */
+};